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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. Hitachi Single-Chip Microcomputer H8/3834U Series HD6433833U HD6473834U, HD6433834U HD6433835U HD6433836U HD6473837U, HD6433837U Hardware Manual ADE-602-089 Preface The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3834U Series has a system-on-a-chip architecture that includes such peripheral functions as an LCD controller/driver, five types of timers, a 14-bit PWM, a three-channel serial communication interface, and an A/D converter. This makes it ideal for use in systems requiring an LCD display. This manual describes the hardware of the H8/3834U Series. For details on the H8/3834U Series instruction set, refer to the H8/300L Series Programming Manual. Contents Section 1 1.1 1.2 1.3 Overview.......................................................................................................... Overview......................................................................................................................... Internal Block Diagram .................................................................................................. Pin Arrangement and Functions ..................................................................................... 1.3.1 Pin Arrangement................................................................................................. 1.3.2 Pin Functions ...................................................................................................... 1 1 5 6 6 8 Section 2 2.1 CPU................................................................................................................... 13 13 13 14 14 15 15 15 17 17 18 19 20 20 22 26 28 30 31 31 33 37 39 40 42 42 43 45 45 46 46 46 2.2 2.3 2.4 2.5 2.6 2.7 Overview......................................................................................................................... 2.1.1 Features............................................................................................................... 2.1.2 Address Space..................................................................................................... 2.1.3 Register Configuration........................................................................................ Register Descriptions...................................................................................................... 2.2.1 General Registers................................................................................................ 2.2.2 Control Registers ................................................................................................ 2.2.3 Initial Register Values......................................................................................... Data Formats................................................................................................................... 2.3.1 Data Formats in General Registers ..................................................................... 2.3.2 Memory Data Formats ........................................................................................ Addressing Modes .......................................................................................................... 2.4.1 Addressing Modes .............................................................................................. 2.4.2 Effective Address Calculation ............................................................................ Instruction Set................................................................................................................. 2.5.1 Data Transfer Instructions .................................................................................. 2.5.2 Arithmetic Operations ........................................................................................ 2.5.3 Logic Operations ................................................................................................ 2.5.4 Shift Operations .................................................................................................. 2.5.5 Bit Manipulations ............................................................................................... 2.5.6 Branching Instructions........................................................................................ 2.5.7 System Control Instructions ............................................................................... 2.5.8 Block Data Transfer Instruction ......................................................................... Basic Operational Timing............................................................................................... 2.6.1 Access to On-Chip Memory (RAM, ROM) ....................................................... 2.6.2 Access to On-Chip Peripheral Modules ............................................................. CPU States ...................................................................................................................... 2.7.1 Overview............................................................................................................. 2.7.2 Program Execution State ................................................................................... 2.7.3 Program Halt State.............................................................................................. 2.7.4 Exception-Handling State................................................................................... 2.8 2.9 Memory Map .................................................................................................................. 2.8.1 Memory Map ...................................................................................................... 2.8.2 LCD RAM Address Relocation.......................................................................... Application Notes ........................................................................................................... 2.9.1 Notes on Data Access ......................................................................................... 2.9.2 Notes on Bit Manipulation.................................................................................. 2.9.3 Notes on Use of the EEPMOV Instruction ......................................................... 47 47 52 53 53 55 61 Section 3 3.1 3.2 Exception Handling...................................................................................... 63 63 63 63 63 65 66 66 68 77 78 79 84 85 85 86 3.3 3.4 Overview......................................................................................................................... Reset ............................................................................................................................ 3.2.1 Overview............................................................................................................. 3.2.2 Reset Sequence ................................................................................................... 3.2.3 Interrupt Immediately after Reset....................................................................... Interrupts......................................................................................................................... 3.3.1 Overview............................................................................................................. 3.3.2 Interrupt Control Registers ................................................................................. 3.3.3 External Interrupts .............................................................................................. 3.3.4 Internal Interrupts ............................................................................................... 3.3.5 Interrupt Operations............................................................................................ 3.3.6 Interrupt Response Time..................................................................................... Application Notes ........................................................................................................... 3.4.1 Notes on Stack Area Use .................................................................................... 3.4.2 Notes on Rewriting Port Mode Registers ........................................................... Section 4 4.1 Clock Pulse Generators............................................................................... 89 89 89 89 90 93 96 97 4.2 4.3 4.4 4.5 Overview......................................................................................................................... 4.1.1 Block Diagram.................................................................................................... 4.1.2 System Clock and Subclock ............................................................................... System Clock Generator ................................................................................................. Subclock Generator ........................................................................................................ Prescalers ........................................................................................................................ Note on Oscillators ......................................................................................................... Section 5 5.1 5.2 5.3 Power-Down Modes..................................................................................... 99 Overview......................................................................................................................... 99 5.1.1 System Control Registers ................................................................................... 102 Sleep Mode ..................................................................................................................... 105 5.2.1 Transition to Sleep Mode.................................................................................... 105 5.2.2 Clearing Sleep Mode .......................................................................................... 105 Standby Mode................................................................................................................. 106 5.4 5.5 5.6 5.7 5.8 5.3.1 Transition to Standby Mode ............................................................................... 106 5.3.2 Clearing Standby Mode ...................................................................................... 106 5.3.3 Oscillator Settling Time after Standby Mode is Cleared .................................... 106 5.3.4 Transition to Standby Mode and Port Pin States ................................................ 107 Watch Mode.................................................................................................................... 108 5.4.1 Transition to Watch Mode .................................................................................. 108 5.4.2 Clearing Watch Mode ......................................................................................... 108 5.4.3 Oscillator Settling Time after Watch Mode is Cleared ....................................... 108 Subsleep Mode................................................................................................................ 109 5.5.1 Transition to Subsleep Mode .............................................................................. 109 5.5.2 Clearing Subsleep Mode..................................................................................... 109 Subactive Mode .............................................................................................................. 110 5.6.1 Transition to Subactive Mode ............................................................................. 110 5.6.2 Clearing Subactive Mode.................................................................................... 110 5.6.3 Operating Frequency in Subactive Mode ........................................................... 110 Active (medium-speed) Mode ........................................................................................ 111 5.7.1 Transition to Active (medium-speed) Mode....................................................... 111 5.7.2 Clearing Active (medium-speed) Mode ............................................................. 111 5.7.3 Operating Frequency in Active (medium-speed) Mode ..................................... 111 Direct Transfer................................................................................................................ 112 5.8.1 Direct Transfer Overview ................................................................................... 112 5.8.2 Calculation of Direct Transfer Time before Transition ...................................... 113 Section 6 6.1 6.2 ROM.................................................................................................................. 117 6.3 6.4 6.5 6.6 Overview......................................................................................................................... 117 6.1.1 Block Diagram.................................................................................................... 117 H8/3834U PROM Mode ................................................................................................. 118 6.2.1 Setting to PROM Mode ..................................................................................... 118 6.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 118 H8/3834U Programming ................................................................................................ 121 6.3.1 Writing and Verifying ......................................................................................... 121 6.3.2 Programming Precautions................................................................................... 124 H8/3837U PROM Mode ................................................................................................. 125 6.4.1 Setting to PROM Mode ...................................................................................... 125 6.4.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 125 H8/3837U Programming ................................................................................................ 128 6.5.1 Writing and Verifying ......................................................................................... 128 6.5.2 Programming Precautions................................................................................... 133 Reliability of Programmed Data..................................................................................... 134 Section 7 7.1 RAM ................................................................................................................. 135 Overview......................................................................................................................... 135 7.1.1 Block Diagram.................................................................................................... 135 I/O Ports........................................................................................................... 137 8.1 Overview ............................................................................................................................ 137 8.2 Port 1 ............................................................................................................................ 139 8.2.1 Overview............................................................................................................. 139 8.2.2 Register Configuration and Description ............................................................. 139 8.2.3 Pin Functions ...................................................................................................... 143 8.2.4 Pin States ............................................................................................................ 145 8.2.5 MOS Input Pull-Up............................................................................................. 145 8.3 Port 2 ............................................................................................................................ 146 8.3.1 Overview............................................................................................................. 146 8.3.2 Register Configuration and Description ............................................................. 146 8.3.3 Pin Functions ...................................................................................................... 150 8.3.4 Pin States ............................................................................................................ 150 8.4 Port 3 ............................................................................................................................ 151 8.4.1 Overview............................................................................................................. 151 8.4.2 Register Configuration and Description ............................................................. 151 8.4.3 Pin Functions ...................................................................................................... 155 8.4.4 Pin States ............................................................................................................ 157 8.4.5 MOS Input Pull-Up............................................................................................. 157 8.5 Port 4 ............................................................................................................................ 158 8.5.1 Overview............................................................................................................. 158 8.5.2 Register Configuration and Description ............................................................. 158 8.5.3 Pin Functions ...................................................................................................... 160 8.5.4 Pin States ............................................................................................................ 161 8.6 Port 5 ............................................................................................................................ 162 8.6.1 Overview............................................................................................................. 162 8.6.2 Register Configuration and Description ............................................................. 162 8.6.3 Pin Functions ...................................................................................................... 165 8.6.4 Pin States ............................................................................................................ 166 8.6.5 MOS Input Pull-Up............................................................................................. 166 8.7 Port 6 ............................................................................................................................ 167 8.7.1 Overview............................................................................................................. 167 8.7.2 Register Configuration and Description ............................................................. 167 8.7.3 Pin Functions ...................................................................................................... 169 8.7.4 Pin States ............................................................................................................ 169 8.7.5 MOS Input Pull-Up............................................................................................. 170 8.8 Port 7 ............................................................................................................................ 171 Section 8 8.9 8.10 8.11 8.12 8.13 8.8.1 8.8.2 8.8.3 8.8.4 Port 8 8.9.1 8.9.2 8.9.3 8.9.4 Port 9 8.10.1 8.10.2 8.10.3 8.10.4 Port A 8.11.1 8.11.2 8.11.3 8.11.4 Port B 8.12.1 8.12.2 Port C 8.13.1 8.13.2 Overview............................................................................................................. 171 Register Configuration and Description ............................................................. 171 Pin Functions ...................................................................................................... 173 Pin States ............................................................................................................ 173 ............................................................................................................................ 174 Overview............................................................................................................. 174 Register Configuration and Description ............................................................. 174 Pin Functions ...................................................................................................... 176 Pin States ............................................................................................................ 176 ............................................................................................................................ 177 Overview............................................................................................................. 177 Register Configuration and Description ............................................................. 177 Pin Functions ...................................................................................................... 179 Pin States ............................................................................................................ 180 ............................................................................................................................ 181 Overview............................................................................................................. 181 Register Configuration and Description ............................................................. 181 Pin Functions ...................................................................................................... 183 Pin States ............................................................................................................ 184 ............................................................................................................................ 185 Overview............................................................................................................. 185 Register Configuration and Description ............................................................. 185 ............................................................................................................................ 186 Overview............................................................................................................. 186 Register Configuration and Description ............................................................. 186 Section 9 9.1 9.2 9.3 9.4 Timers............................................................................................................... 187 Overview......................................................................................................................... 187 Timer A........................................................................................................................... 188 9.2.1 Overview............................................................................................................. 188 9.2.2 Register Descriptions.......................................................................................... 190 9.2.3 Timer Operation.................................................................................................. 192 9.2.4 Timer A Operation States ................................................................................... 193 Timer B ........................................................................................................................... 194 9.3.1 Overview............................................................................................................. 194 9.3.2 Register Descriptions.......................................................................................... 195 9.3.3 Timer Operation.................................................................................................. 197 9.3.4 Timer B Operation States ................................................................................... 198 Timer C ........................................................................................................................... 199 9.4.1 Overview............................................................................................................. 199 9.4.2 Register Descriptions.......................................................................................... 201 9.5 9.6 9.4.3 Timer Operation.................................................................................................. 204 9.4.4 Timer C Operation States ................................................................................... 205 Timer F ........................................................................................................................... 206 9.5.1 Overview............................................................................................................. 206 9.5.2 Register Descriptions.......................................................................................... 208 9.5.3 Interface with the CPU ....................................................................................... 215 9.5.4 Timer Operation.................................................................................................. 219 9.5.5 Application Notes ............................................................................................... 222 Timer G........................................................................................................................... 224 9.6.1 Overview............................................................................................................. 224 9.6.2 Register Descriptions.......................................................................................... 226 9.6.3 Noise Canceller Circuit....................................................................................... 230 9.6.4 Timer Operation.................................................................................................. 231 9.6.5 Application Notes ............................................................................................... 235 9.6.6 Sample Timer G Application.............................................................................. 239 Section 10 10.1 10.2 10.3 10.4 Serial Communication Interface............................................................. 241 Overview......................................................................................................................... 241 SCI1 ................................................................................................................................ 242 10.2.1 Overview........................................................................................................... 242 10.2.2 Register Descriptions........................................................................................ 244 10.2.3 Operation .......................................................................................................... 249 10.2.4 Interrupts........................................................................................................... 253 10.2.5 Application Notes ............................................................................................. 253 SCI2 ................................................................................................................................ 254 10.3.1 Overview........................................................................................................... 254 10.3.2 Register Descriptions........................................................................................ 256 10.3.3 Operation .......................................................................................................... 262 10.3.4 Interrupts........................................................................................................... 269 10.3.5 Application Notes ............................................................................................. 269 SCI3 ................................................................................................................................ 270 10.4.1 Overview........................................................................................................... 270 10.4.2 Register Descriptions........................................................................................ 273 10.4.3 Operation .......................................................................................................... 291 10.4.4 Operation in Asynchronous Mode.................................................................... 295 10.4.5 Operation in Synchronous Mode ...................................................................... 303 10.4.6 Multiprocessor Communication Function ........................................................ 310 10.4.7 Interrupts........................................................................................................... 316 10.4.8 Application Notes ............................................................................................. 317 14-Bit PWM ................................................................................................. 323 Section 11 11.1 11.2 11.3 Overview......................................................................................................................... 323 11.1.1 Features............................................................................................................. 323 11.1.2 Block Diagram.................................................................................................. 323 11.1.3 Pin Configuration.............................................................................................. 324 11.1.4 Register Configuration...................................................................................... 324 Register Descriptions...................................................................................................... 325 11.2.1 PWM Control Register (PWCR) ...................................................................... 325 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) ........................................ 326 Operation ........................................................................................................................ 327 Section 12 12.1 12.2 12.3 12.4 12.5 12.6 A/D Converter.............................................................................................. 329 Overview......................................................................................................................... 329 12.1.1 Features............................................................................................................. 329 12.1.2 Block Diagram.................................................................................................. 329 12.1.3 Pin Configuration.............................................................................................. 330 12.1.4 Register Configuration...................................................................................... 330 Register Descriptions...................................................................................................... 331 12.2.1 A/D Result Register (ADRR) ........................................................................... 331 12.2.2 A/D Mode Register (AMR) .............................................................................. 331 12.2.3 A/D Start Register (ADSR) .............................................................................. 333 Operation ........................................................................................................................ 334 12.3.1 A/D Conversion Operation ............................................................................... 334 12.3.2 Start of A/D Conversion by External Trigger Input ......................................... 334 Interrupts......................................................................................................................... 335 Typical Use ..................................................................................................................... 335 Application Notes ........................................................................................................... 338 LCD Controller/Driver .............................................................................. 339 Overview......................................................................................................................... 339 13.1.1 Features............................................................................................................. 339 13.1.2 Block Diagram.................................................................................................. 340 13.1.3 Pin Configuration.............................................................................................. 341 13.1.4 Register Configuration...................................................................................... 341 Register Descriptions...................................................................................................... 342 13.2.1 LCD Port Control Register (LPCR) ................................................................. 342 13.2.2 LCD Control Register (LCR) ........................................................................... 344 Operation ........................................................................................................................ 346 13.3.1 Settings Prior to LCD Display.......................................................................... 346 13.3.2 Relation of LCD RAM to Display.................................................................... 347 13.3.3 Connection to HD66100 ................................................................................... 348 13.3.4 Operation in Power-Down Modes .................................................................... 356 Section 13 13.1 13.2 13.3 13.3.5 Boosting the LCD Driver Power Supply .......................................................... 357 Section 14 14.1 14.2 14.3 14.4 14.5 Electrical Characteristics .......................................................................... 359 H8/3834U Series Absolute Maximum Ratings .............................................................. 359 H8/3833U and H8/3834U Electrical Characteristics...................................................... 360 14.2.1 Power Supply Voltage and Operating Range.................................................... 360 14.2.2 DC Characteristics ............................................................................................ 362 14.2.3 AC Characteristics ............................................................................................ 367 14.2.4 A/D Converter Characteristics.......................................................................... 370 14.2.5 LCD Characteristics.......................................................................................... 371 H8/3835U, H8/3836U, and H8/3837U Electrical Characteristics.................................. 372 14.3.1 Power Supply Voltage and Operating Range.................................................... 372 14.3.2 DC Characteristics ............................................................................................ 374 14.3.3 AC Characteristics ............................................................................................ 379 14.3.4 A/D Converter Characteristics.......................................................................... 382 14.3.5 LCD Characteristics.......................................................................................... 383 Operation Timing............................................................................................................ 384 Output Load Circuit........................................................................................................ 389 Instructions ..................................................................................................................... 391 Operation Code Map....................................................................................................... 399 Number of Execution States ........................................................................................... 401 Appendix A CPU Instruction Set.................................................................................. 391 A.1 A.2 A.3 Appendix B On-Chip Registers..................................................................................... 408 B.1 B.2 I/O Registers (1) ............................................................................................................. 408 I/O Registers (2) ............................................................................................................. 411 Appendix C I/O Port Block Diagrams ........................................................................ 454 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Schematic Diagram of Port 1.......................................................................................... Schematic Diagram of Port 2.......................................................................................... Schematic Diagram of Port 3.......................................................................................... Schematic Diagram of Port 4.......................................................................................... Schematic Diagram of Port 5.......................................................................................... Schematic Diagram of Port 6.......................................................................................... Schematic Diagram of Port 7.......................................................................................... Schematic Diagram of Port 8.......................................................................................... Schematic Diagram of Port 9.......................................................................................... 454 459 462 468 471 472 473 474 475 C.10 C.11 C.12 Schematic Diagram of Port A......................................................................................... 476 Schematic Diagram of Port B ......................................................................................... 477 Schematic Diagram of Port C ......................................................................................... 477 Appendix D Port States in the Different Processing States .................................. 478 Appendix E Appendix F Product Code Lineup ............................................................................... 479 Package Dimensions ................................................................................ 481 Section 1 Overview 1.1 Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3834U Series features an on-chip liquid crystal display (LCD) controller/driver. Other on-chip peripheral functions include five timers, a 14-bit pulse width modulator (PWM), three serial communication interface channels, and an analog-to-digital (A/D) converter. Together these functions make the H8/3834U Series ideally suited for embedded control of systems requiring an LCD display. The H8/3834U Series, in particular, features low-voltage A/D converter operation (VCC = AVCC = 2.7 V to 5.5 V), enabling these devices to be used in low-voltage, single power supply systems. On-chip memory is 24 kbytes of ROM and 1 kbyte of RAM in the H8/3833U, 32 kbytes of ROM and 1 kbyte of RAM in the H8/3834U, 40 kbytes of ROM and 2 kbytes of RAM in the H8/3835U, 48 kbytes of ROM and 2 kbytes of RAM in the H8/3836U, and 60 kbytes of ROM and 2 kbytes of RAM in the H8/3837U. The H8/3834U and H8/3837U both include a ZTATTM version*, featuring a user-programmable on-chip PROM. Table 1-1 summarizes the features of the H8/3834U Series. Note: * ZTAT is a trademark of Hitachi, Ltd. Table 1-1 Features Item CPU Description High-speed H8/300L CPU * General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) * Operating speed -- Max. operating speed: 5 MHz -- Add/subtract: 0.4 s (operating at 5 MHz) -- Multiply/divide: 2.8 s (operating at 5 MHz) -- Can run on 32.768 kHz subclock * Instruction set compatible with H8/300 CPU -- Instruction length of 2 bytes or 4 bytes -- Basic arithmetic operations between registers -- MOV instruction for data transfer between memory and registers 1 Table 1-1 Features (cont) Item CPU Description Typical instructions * Multiply (8 bits x 8 bits) * Divide (16 bits / 8 bits) * Bit accumulator * Register-indirect designation of bit position Interrupts * 13 external interrupt pins: IRQ4 to IRQ0, WKP7 to WKP0 * 20 internal interrupt sources Clock pulse generators Two on-chip clock pulse generators * System clock pulse generator: 1 to 10 MHz * Subclock pulse generator: 32.768 kHz Power-down modes Six power-down modes * Sleep mode * Standby mode * Watch mode * Subsleep mode * Subactive mode * Active (medium-speed) mode Memory Large on-chip memory * H8/3833U: 24-kbyte ROM, 1-kbyte RAM * H8/3834U: 32-kbyte ROM, 1-kbyte RAM * H8/3835U: 40-kbyte ROM, 2-kbyte RAM * H8/3836U: 48-kbyte ROM, 2-kbyte RAM * H8/3837U: 60-kbyte ROM, 2-kbyte RAM I/O ports * I/O pins: 71 * Input pins: 13 Timers Five on-chip timers * Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (o)* and four clock signals divided from the watch clock (ow)* 2 Table 1-1 Features (cont) Item Timers Description * Timer B: 8-bit timer -- Count-up timer with selection of seven internal clock signals or event input from external pin -- Auto-reloading * Timer C: 8-bit timer -- Count-up/count-down timer with selection of seven internal clock signals or event input from external pin -- Auto-reloading * Timer F: 16-bit timer -- Can be used as two independent 8-bit timers. -- Count-up timer with selection of four internal clock signals or event input from external pin -- Compare-match function with toggle output * Timer G: 8-bit timer -- Count-up timer with selection of four internal clock signals -- Input capture function with built-in noise canceller circuit Note: * o and ow are defined in section 4, Clock Pulse Generators. Serial communication interface Three channels on chip * SCI1: synchronous serial interface Choice of 8-bit or 16-bit data transfer * SCI2: 8-bit synchronous serial interface Automatic transfer of 32-byte data segments * SCI3: 8-bit synchronous or asynchronous serial interface Built-in function for multiprocessor communication 14-bit PWM Pulse-division PWM output for reduced ripple * Can be used as a 14-bit D/A converter by connecting to an external low-pass filter. A/D converter * Successive approximations using a resistance ladder * Resolution: 8 bits * 12-channel analog input port * Conversion time: 31/o or 62/o per channel 3 Table 1-1 Features (cont) Item LCD controller/driver Specification Up to 40 segment pins and 4 common pins * Choice of four duty cycles (static, 1/2, 1/3, 1/4) * Segments can be expanded externally * Segment pins can be switched to general-purpose ports in groups of four Product lineup Product Code Mask ROM Version ZTATTM Version Package 100-pin QFP (FP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) ROM: 32 kbytes RAM: 1 kbyte ROM/RAM Size ROM: 24 kbytes RAM: 1 kbyte HD6433833UH -- HD6433833UF -- HD6433833UX -- HD6433834UH HD6473834UH 100-pin QFP (FP-100B) HD6433834UF HD6473834UF 100-pin QFP (FP-100A) HD6433834UX HD6473834UX 100-pin TQFP (TFP-100B) HD6433835UH -- HD6433835UF -- HD6433835UX -- HD6433836UH -- HD6433836UF -- HD6433836UX -- 100-pin QFP (FP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) ROM: 40 kbytes RAM: 2 kbytes ROM: 48 kbytes RAM: 2 kbytes HD6433837UH HD6473837UH 100-pin QFP (FP-100B) HD6433837UF HD6473837UF 100-pin QFP (FP-100A) HD6433837UX HD6473837UX 100-pin TQFP (TFP-100B) ROM: 60 kbytes RAM: 2 kbytes 4 1.2 Internal Block Diagram Figure 1-1 shows a block diagram of the H8/3834U Series. OSC1 OSC2 System clock pulse generator TEST MD0 RES VCC VCC VSS VSS P10/TMOW P11/TMOFL P12/TMOFH P13/TMIG P14/PWM P15/IRQ1/TMIB P16/IRQ2/TMIC P1 7/IRQ3/TMIF Port 1 Subclock pulse generator X1 X2 CPU H8/300L LCD driver power supply V1 V2 V3 PA3/COM4 Data bus (lower) Data bus (upper) Port A Address bus PA2/COM3 PA1/COM2 PA0/COM1 P97/SEG40/CL1 P96/SEG39/CL2 P20/IRQ4/ADTRG P21/UD P22 P23 P24 P25 P26 P27 Port 2 ROM RAM Port 9 P95/SEG38/DO P94/SEG37/M P93/SEG36 P92/SEG35 P91/SEG34 P90/SEG33 Timer A LCD controller Timer B P30/SCK1 P31/SI1 P32/SO1 P33/SCK2 P34/SI2 P35/SO2 P36/STRB P37/CS P40/SCK3 P41/RXD P42/TXD P43/IRQ0 Port 4 Port 3 Timer F SCI1 P87/SEG32 P86/SEG31 P85/SEG30 Port 8 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 Timer C SCI2 SCI3 Timer G 14-bit PWM P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 A/D converter P50/WKP0 /SEG1 P51/WKP1 /SEG2 P52/WKP2 /SEG3 P53/WKP3 /SEG4 P54/WKP4 /SEG5 P55/WKP5 /SEG6 P56/WKP6 /SEG7 P57/WKP7 /SEG8 Port 5 Port B Port C Port 7 P67/SEG16 P66/SEG15 P65/SEG14 Port 6 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 AVCC AVSS Figure 1-1 Block Diagram 5 PC0/AN8 PC1/AN9 PC2/AN10 PC3/AN11 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3834U Series pin arrangement is shown in figures 1-2 and 1-3. P16/IRQ2/TMIC P17/IRQ3/TMIF P15/IRQ1/TMIB P12/TMOFH P11/TMOFL 78 PC2/AN10 P43/IRQ0 P42/TXD PC1/AN9 PC0/AN8 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 AVCC P14/PWM P10/TMOW 77 P13/TMIG P40/SCK3 P41/RXD 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 100 76 VCC PC3/AN11 AVSS TEST X2 X1 VSS OSC1 OSC2 RES MD0 P20/IRQ4/ADTRG P21/UD P22 P23 P24 P25 P26 P27 P30/SCK1 P31/SI1 P32/SO1 P33/SCK2 P34/SI2 P35/SO2 P36/STRB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P97/SEG40/CL1 P96/SEG39/CL2 P95/SEG38/D0 P94/SEG37/M P93/SEG36 P92/SEG35 P91/SEG34 P90/SEG33 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 P64/SEG13 49 P65/SEG14 P37/CS VCC P61/SEG10 P62/SEG11 P63/SEG12 P50/WKP0 /SEG1 P51/WKP1 /SEG2 P52/WKP2 /SEG3 P53/WKP3 /SEG4 P54/WKP4 /SEG5 P55/WKP5 /SEG6 P56/WKP6 /SEG7 P57/WKP7 /SEG8 Figure 1-2 Pin Arrangement (FP-100B, TFP-100B: Top View) 6 P66/SEG15 VSS V3 V2 V1 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P60/SEG9 50 P16 /IRQ2 /TMIC P15 /IRQ1 /TMIB P17 /IRQ3 /TMIF P12 /TMOFH 82 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 PC0 /AN 8 PC1 /AN 9 PC2 /AN10 PC3 /AN11 AVSS TEST X2 X1 VSS OSC 1 OSC 2 RES MD0 P20 /IRQ4 /ADTRG P21 /UD P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P30 /SCK 1 P31 /SI 1 P32 /SO 1 P33 /SCK 2 P34 /SI 2 P35 /SO 2 P36 /STRB P37 /CS VSS 81 P11 /TMOFL P40 /SCK 3 P13 /TMIG P14 /PWM P43 /IRQ0 P41 /RXD P42 /TXD PB7 /AN7 PB6 /AN6 PB5 /AN5 PB4 /AN4 PB3 /AN3 PB2 /AN2 PB1 /AN1 PB0 /AN0 AVCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10 /TMOW VCC P97 /SEG40 /CL 1 P96 /SEG39 /CL 2 P95 /SEG38 /DO P94 /SEG37 /M P93 /SEG36 P92 /SEG35 P91 /SEG34 P90 /SEG33 P87 /SEG32 P86 /SEG31 P85 /SEG30 P84 /SEG29 P83 /SEG28 P82 /SEG27 P81 /SEG26 P80 /SEG25 P77 /SEG24 P76 /SEG23 P75 /SEG22 P74 /SEG21 P73 /SEG20 P72 /SEG19 P71 /SEG18 P70 /SEG17 P67 /SEG16 P66 /SEG15 P65 /SEG14 P64 /SEG13 V3 V2 V1 VCC PA3 /COM 4 PA2 /COM 3 PA1 /COM 2 PA0 /COM 1 P50 /WKP0 /SEG 1 P51 /WKP1 /SEG 2 P52 /WKP2 /SEG 3 P53 /WKP3 /SEG 4 P54 /WKP4 /SEG 5 P55 /WKP5 /SEG 6 P56 /WKP6 /SEG 7 P57 /WKP7 /SEG 8 P60 /SEG 9 P61 /SEG10 P62 /SEG11 Figure 1-3 Pin Arrangement (FP-100A: Top View) 7 P63 /SEG12 1.3.2 Pin Functions Table 1-2 outlines the pin functions of the H8/3834U Series. Table 1-2 Pin Functions Pin No. Type Symbol FP-100B 31, 76 FP-100A 34, 79 I/O Input Name and Functions Power supply: All VCC pins should be connected to the system power supply (+5 V) Ground: All VSS pins should be connected to the system power supply (0 V) Analog power supply: This is the power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). Analog ground: This is the A/D converter ground pin. It should be connected to the system power supply (0 V). LCD power supply: These are power supply pins for the LCD controller/ driver. A built-in resistor divider is provided for the power supply, so these pins are normally left open. Power supply conditions are VCC V1 V2 V3 VSS. System clock: This pin connects to a crystal or ceramic oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram. Subclock: This pin connects to a 32.768-kHz crystal oscillator. See section 4, Clock Pulse Generators, for a typical connection diagram. Power VCC source pins VSS 6, 27 9, 30 Input AVCC 89 92 Input AVSS 2 5 Input V1, V2, V3 30, 29, 28 33, 32, 31 Input Clock pins OSC1 OSC2 7 8 10 11 Input Output X1 X2 5 4 8 7 Input Output 8 Table 1-2 Pin Functions (cont) Pin No. Type System control Symbol RES MD0 TEST FP-100B 9 10 3 FP-100A 12 13 6 I/O Input Input Input Name and Functions Reset: When this pin is driven low, the chip is reset Mode: This pin controls system clock oscillation in the reset state Test: This is a test pin, not for use in application systems. It should be connected to VSS. External interrupt request 0 to 4: These are input pins for external interrupts for which there is a choice between rising and falling edge sensing Wakeup interrupt request 0 to 7: These are input pins for external interrupts that are detected at the falling edge Clock output: This is an output pin for waveforms generated by the timer A output circuit Timer B event counter input: This is an event input pin for input to the timer B counter Timer C event counter input: This is an event input pin for input to the timer C counter Timer C up/down select: This pin selects whether the timer C counter is used for up- or down-counting. At high level it selects up-counting, and at low level down-counting. Timer F event counter input: This is an event input pin for input to the timer F counter Interrupt pins IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP7 to WKP0 88 82 83 84 11 43 to 36 91 85 86 87 14 46 to 39 Input Input Timer pins TMOW 77 80 Output TMIB 82 85 Input TMIC 83 86 Input UD 12 15 Input TMIF 84 87 Input 9 Table 1-2 Pin Functions (cont) Pin No. Type Timer pins Symbol TMOFL FP-100B 78 FP-100A 81 I/O Output Name and Functions Timer FL output: This is an output pin for waveforms generated by the timer FL output compare function Timer FH output: This is an output pin for waveforms generated by the timer FH output compare function Timer G capture input: This is an input pin for the timer G input capture function 14-bit PWM output: This is an output pin for waveforms generated by the 14-bit PWM Port B: This is an 8-bit input port Port C: This is a 4-bit input port Port 4 (bit 3): This is a 1-bit input port Port 4 (bits 2 to 0): This is a 3-bit I/O port. Input or output can be designated for each bit by means of port control register 4 (PCR4). Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). Port 1: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 1 (PCR1). Port 2: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 2 (PCR2). Port 3: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 3 (PCR3). TMOFH 79 82 Output TMIG 80 83 Input 14-bit PWM pin I/O ports PWM 81 84 Output PB7 to PB0 PC3 to PC0 P43 P42 to P40 97 to 90 1, 100 to 98 88 87 to 85 100 to 93 4 to 1 91 90 to 88 Input Input Input I/O PA3 to PA0 32 to 35 35 to 38 I/O P17 to P10 84 to 77 87 to 80 I/O P27 to P20 18 to 11 21 to 14 I/O P37 to P30 26 to 19 29 to 22 I/O 10 Table 1-2 Pin Functions (cont) Pin No. Type I/O ports Symbol P57 to P50 FP-100B 43 to 36 FP-100A 46 to 39 I/O I/O Name and Functions Port 5: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 5 (PCR5). Port 6: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 6 (PCR6). Port 7: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7). Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8). Port 9: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 9 (PCR9). SCI1 receive data input: This is the SCI1 data input pin SCI1 send data output: This is the SCI1 data output pin SCI1 clock I/O : This is the SCI1 clock I/O pin SCI2 receive data input: This is the SCI2 data input pin SCI2 send data output: This is the SCI2 data output pin SCI2 clock I/O : This is the SCI2 clock I/O pin SCI2 chip select input: This pin controls the start of SCI2 transfers SCI2 strobe output: This pin outputs a strobe pulse each time a byte of data is transferred P67 to P60 51 to 44 54 to 47 I/O P77 to P70 59 to 52 62 to 55 I/O P87 to P80 67 to 60 70 to 63 I/O P97 to P90 75 to 68 78 to 71 I/O Serial communication interface (SCI) SI1 SO1 SCK1 SI2 SO2 SCK2 CS 20 21 19 23 24 22 26 23 24 22 26 27 25 29 Input Output I/O Input Output I/O Input STRB 25 28 Output 11 Table 1-2 Pin Functions (cont) Pin No. Type Serial communication interface (SCI) Symbol RXD TXD SCK3 A/D converter AN11 to AN0 ADTRG FP-100B 86 87 85 1, 100 to 90 11 FP-100A 89 90 88 4 to 1 100 to 93 14 I/O Input Output I/O Input Name and Functions SCI3 receive data input: This is the SCI3 data input pin SCI3 send data output: This is the SCI3 data output pin SCI3 clock I/O : This is the SCI3 clock I/O pin Analog input channels 0 to 11: These are analog data input channels to the A/D converter A/D converter trigger input: This is the external trigger input pin to the A/D converter LCD common output: These are LCD common output pins LCD segment output: These are LCD segment output pins LCD latch clock: This is the display data latch clock output pin for external segment expansion LCD shift clock: This is the display data shift clock output pin for external segment expansion LCD serial data output: This is the serial display data output pin for external segment expansion LCD alternating signal output: This is the LCD alternating signal output pin for external segment expansion Input LCD controller/ driver COM4 to COM1 SEG40 to SEG1 CL1 35 to 32 75 to 36 75 38 to 35 78 to 39 78 Output Output Output CL2 74 77 Output DO 73 76 Output M 72 75 Output 12 Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. * General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit general registers Instruction set with 55 basic instructions, including: -- Multiply and divide instructions -- Powerful bit-manipulation instructions Eight addressing modes -- Register direct -- Register indirect -- Register indirect with displacement -- Register indirect with post-increment or pre-decrement -- Absolute address -- Immediate -- Program-counter relative -- Memory indirect 64-kbyte address space High-speed operation -- All frequently used instructions are executed in two to four states -- High-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.4 s* 8 x 8-bit multiply: 2.8 s* 16 / 8-bit divide: 2.8 s* Low-power operation modes SLEEP instruction for transfer to low-power operation * * * * * Note: * These values are at o = 5 MHz. 13 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack Pointer 0 Control registers (CR) 15 PC 76543210 CCR I U H U N Z V C 0 PC: Program Counter CCR: Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit Figure 2-1 CPU Registers 14 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-2, SP (R7) points to the top of the stack. Lower address side [H'0000] Unused area SP (R7) Stack area Upper address side [H'FFFF] Figure 2-2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0). 15 Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6--User Bit (U): Can be used freely by the user. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4--User Bit (U): Can be used freely by the user. Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 16 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. * * * 17 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. 7 Data Format 0 1-bit data RnH 7 6 5 4 3 2 1 0 don't care 7 0 1-bit data RnL don't care 7 6 5 4 3 2 1 0 7 0 LSB Byte data RnH MSB don't care 7 0 LSB Byte data RnL don't care MSB 15 0 LSB Word data Rn MSB 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnH don't care 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnL don't care Notation: RnH: Upper byte of general register RnL: Lower byte of general register MSB: Most significant bit LSB: Least significant bit Figure 2-3 Register Data Formats 18 2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching. Data Type Address Data Format 7 0 1-bit data Byte data Address n Address n Even address Odd address Even address Odd address Even address Odd address 7 MSB 6 5 4 3 2 1 0 LSB Word data MSB Upper 8 bits Lower 8 bits LSB Byte data (CCR) on stack MSB MSB CCR CCR* LSB LSB Word data on stack MSB LSB CCR: Condition code register Note: * Ignored on return Figure 2-4 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. 19 2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. 1 2 3 4 5 6 7 8 Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8 1. Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. 2. Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. Register Indirect with Displacement--@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. 3. 20 4. Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. 5. Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). 6. Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. Program-Counter Relative--@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. The displacement should be an even number. 21 8. Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2-2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position. 22 Table 2-2 Effective Address Calculation Effective Address Calculation Method 3 0 3 No. rm 43 0 Addressing Mode and Instruction Format Effective Address (EA) rn 1 Register direct, Rn 0 15 87 op 15 0 rm Contents (16 bits) of register indicated by rm 15 43 0 rn Operand is contents of registers indicated by rm/rn 0 2 Register indirect, @Rn 15 76 op 15 0 rm 3 Contents (16 bits) of register indicated by rm 43 0 Register indirect with displacement, @(d:16, Rn) rm disp 15 0 23 15 15 76 op disp 0 15 0 4 43 0 Register indirect with post-increment, @Rn+ rm Contents (16 bits) of register indicated by rm 15 76 op 15 1 or 2 0 Register indirect with pre-decrement, @-Rn 43 0 Contents (16 bits) of register indicated by rm 15 0 15 76 op rm Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size Table 2-2 Effective Address Calculation (cont) Effective Address Calculation Method 15 87 No. H'FF 0 Addressing Mode and Instruction Format Effective Address (EA) 5 Absolute address @aa:8 abs 15 0 0 15 87 op @aa:16 0 15 op abs 6 0 Immediate #xx:8 IMM Operand is 1- or 2-byte immediate data 0 24 15 15 87 op #xx:16 15 op IMM 0 7 Program-counter relative @(d:8, PC) PC contents 15 0 15 87 0 Sign extension disp op disp Table 2-2 Effective Address Calculation (cont) Effective Address Calculation Method Effective Address (EA) No. Addressing Mode and Instruction Format 8 0 Memory indirect, @@aa:8 15 87 op 15 87 0 abs H'00 15 abs 0 Memory contents (16 bits) 25 Notation: rm, rn: Register field Operation field op: disp: Displacement IMM: Immediate data abs: Absolute address 2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Instructions MOV, PUSH*1, POP*1 Number 1 14 4 8 14 5 8 1 Total: 55 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. 2. Bcc is a conditional branch instruction in which cc represents a condition code. ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. 26 Notation Rd Rs Rn (EAd), 27 2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction MOV Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. PUSH W Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. Notes: * Size: Operand size B: Byte W: Word Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details. 28 15 8 7 0 MOV RmRn op 15 8 7 rm rn 0 op 15 8 7 rm rn 0 @RmRn op disp 15 8 7 rm rn @(d:16, Rm)Rn 0 op 15 8 7 rm rn 0 @Rm+Rn, or Rn @-Rm op 15 rn 8 7 abs 0 @aa:8Rn op abs 15 8 7 rn @aa:16Rn 0 op 15 rn 8 7 IMM 0 #xx:8Rn op IMM 15 8 7 rn #xx:16Rn 0 op Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data 1 1 1 rn PUSH, POP @SP+ Rn, or Rn @-SP Figure 2-5 Data Transfer Instruction Codes 29 2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction ADD SUB Size* B/W Function Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. Rd 1 Rd Increments or decrements a general register Rd 1 Rd, Rd 2 Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and the result is stored in the CCR. Word data can be compared only between two general registers. 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register ADDX SUBX B INC DEC ADDS SUBS DAA DAS MULXU B W B B DIVXU B CMP B/W NEG B Notes: * Size: Operand size B: Byte W: Word 30 2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction AND Size* B Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B ~ Rd Rd Obtains the one's complement (logical complement) of general register contents Notes: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2-7 describes the eight shift instructions. Table 2-7 Shift Instructions Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size* B Function Rd shift Rd Performs an arithmetic shift operation on general register contents B Rd shift Rd Performs a logical shift operation on general register contents B Rd rotate Rd Rotates general register contents B Rd rotate through carry Rd Rotates general register contents through the C (carry) bit Notes: * Size: Operand size B: Byte 31 Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 8 7 0 op 15 8 7 rm rn 0 ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 0 op 15 8 7 rn op 15 8 7 rm rn 0 MULXU, DIVXU op 15 rn 8 7 IMM 0 ADD, ADDX, SUBX, CMP (#XX:8) op 15 8 7 rm rn 0 AND, OR, XOR (Rm) op 15 rn 8 7 IMM 0 AND, OR, XOR (#xx:8) op Notation: op: Operation field rm, rn: Register field IMM: Immediate data rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes 32 2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction BSET Size* B Function 1 ( 33 Table 2-8 Bit-Manipulation Instructions (cont) Instruction BXOR Size* B Function C ( Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for details. 34 BSET, BCLR, BNOT, BTST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) 0 op 15 8 7 rm rn op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op 15 8 7 rn rm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 register direct (Rm) op op 15 8 7 abs IMM 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: 0 immediate (#xx:3) op op rm abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes 35 BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont) 36 2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Bcc Size -- Function Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS -- -- -- -- Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Branches unconditionally to a specified address Branches to a subroutine at a specified displacement from the current address Branches to a subroutine at a specified address Returns from a subroutine 37 15 8 7 0 op 15 cc 8 7 disp 0 Bcc op 15 8 7 rm 0 0 0 0 0 JMP (@Rm) op abs 15 8 7 0 JMP (@aa:16) op 15 8 7 abs 0 JMP (@@aa:8) op 15 8 7 disp 0 BSR op 15 8 7 rm 0 0 0 0 0 JSR (@Rm) op abs 15 8 7 0 JSR (@aa:16) op 15 8 7 abs 0 JSR (@@aa:8) op Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address RTS Figure 2-8 Branching Instruction Codes 38 2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction RTE SLEEP LDC Size* -- -- B Function Returns from an exception-handling routine Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register ANDC B CCR #IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR #IMM CCR Logically ORs the condition code register with immediate data XORC B CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data NOP -- PC + 2 PC Only increments the program counter Notes: * Size: Operand size B: Byte 39 15 8 7 0 op 15 8 7 0 RTE, SLEEP, NOP op 15 8 7 rn 0 LDC, STC (Rn) op IMM ANDC, ORC, XORC, LDC (#xx:8) Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction Instruction EEPMOV Size -- Function If R4L 0 then repeat until else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: Size of block (bytes) R5: R6: Starting source address Starting destination address @R5+ @R6+ R4L - 1 R4L R4L = 0 Execution of the next instruction starts as soon as the block transfer is completed. Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the EEPMOV Instruction, for details. 40 15 8 7 0 op op Notation: op: Operation field Figure 2-10 Block Data Transfer Instruction Code 41 2.6 Basic Operational Timing CPU operation is synchronized by a system clock (o) or a subclock (oSUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of o or oSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2-11 shows the on-chip memory access cycle. Bus cycle T1 state o or o SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-11 On-Chip Memory Access Cycle 42 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Figures 2-12 and 2-13 show the on-chip peripheral module access cycle. Two-state access to on-chip peripheral modules Bus cycle T1 state o or o SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-12 On-Chip Peripheral Module Access Cycle (2-State Access) 43 Three-state access to on-chip peripheral modules Bus cycle T1 state o or o SUB T2 state T3 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Address Read data Write data Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access) 44 2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2-14. Figure 2-15 shows the state transitions. CPU state Reset state The CPU is initialized. Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Low-power modes Program halt state A state in which some or all of the chip functions are stopped to conserve power Sleep mode Standby mode Watch mode Subsleep mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Note: See section 5, Power-Down Modes, for details on the modes and their transitions. Figure 2-14 CPU Operation States 45 Reset cleared Reset state Reset occurs Exception-handling state Reset occurs Reset occurs Interrupt source Exception- Exceptionhandling handling request complete Program halt state SLEEP instruction executed Program execution state Figure 2-15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes. 2.7.3 Program Halt State In the program halt state there are four modes: sleep mode, standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes. 2.7.4 Exception-Handling State The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see section 3, Exception Handling. 46 2.8 Memory Map 2.8.1 Memory Map Figure 2-16 (a) shows the H8/3833U memory map. Figure 2-16 (b) shows the H8/3834U memory map. Figure 2-16 (c) shows the H8/3835U memory map. Figure 2-16 (d) shows the H8/3836U memory map. Figure 2-16 (e) shows the H8/3837U memory map. H'0000 Interrupt vector area H'0029 H'002A 24 kbytes (24,576 bytes) On-chip ROM H'5FFF Reserved H'F740 LCD RAM * (64 bytes) H'F77F Reserved H'FB80 On-chip RAM H'FF7F H'FF80 H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Note: * The LCD RAM addresses are the addresses after a reset. 32-byte serial data buffer 1,024 bytes Figure 2-16 (a) H8/3833U Memory Map 47 H'0000 Interrupt vector area H'0029 H'002A 32 kbytes (32,768 bytes) On-chip ROM H'7FFF Reserved H'F740 LCD RAM * (64 bytes) H'F77F Reserved H'FB80 On-chip RAM H'FF7F H'FF80 H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Note: * The LCD RAM addresses are the addresses after a reset. 32-byte serial data buffer 1,024 bytes Figure 2-16 (b) H8/3834U Memory Map 48 H'0000 Interrupt vector area H'0029 H'002A 40 kbytes (40,960 bytes) On-chip ROM H'9FFF Reserved H'F740 LCD RAM * (64 bytes) H'F77F H'F780 On-chip RAM 2,048 bytes H'FF7F H'FF80 32-byte serial data buffer H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Note: * The LCD RAM addresses are the addresses after a reset. Figure 2-16 (c) H8/3835U Memory Map 49 H'0000 Interrupt vector area H'0029 H'002A 48 kbytes (49,152 bytes) On-chip ROM H'BFFF Reserved H'F740 LCD RAM * (64 bytes) H'F77F H'F780 On-chip RAM 2,048 bytes H'FF7F H'FF80 32-byte serial data buffer H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Note: * The LCD RAM addresses are the addresses after a reset. Figure 2-16 (d) H8/3836U Memory Map 50 H'0000 Interrupt vector area H'0029 H'002A 60 kbytes (60,928 bytes) On-chip ROM H'EDFF Reserved H'F740 LCD RAM * (64 bytes) H'F77F H'F780 On-chip RAM 2,048 bytes H'FF7F H'FF80 32-byte serial data buffer H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Note: * The LCD RAM addresses are the addresses after a reset. Figure 2-16 (e) H8/3837U Memory Map 51 2.8.2 LCD RAM Address Relocation After a reset, the LCD RAM area is located at addresses H'F740 to H'F77F. However, this area can be relocated by setting the LCD RAM relocation register (RLCTR) bits. The LCD RAM relocation register is explained below. LCD RAM relocation register (RLCTR: H'FFCF) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 RLCT1 0 R/W 0 RLCT0 0 R/W RLCTR is an 8-bit read/write register that selects the LCD RAM address space. Upon reset, RLCTR is initialized to H'FC. Bits 7 to 2: Reserved bits Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. Bits 1 and 0: LCD RAM relocation select (RLCT1, RLCT0) Bits 1 and 0 select the LCD RAM address space. Bit 1 RLCT1 0 0 1 1 Bit 0 RLCT0 0 1 0 1 Description H'F740 toH'F77F H'F940 to H'F97F*2 H'FB40 to H'FB7F*2 H'FD40 to H'FD7F*1, 2 (initial value) Notes: 1. In devices with 1,024-byte RAM, if RLCT1 to 0 are set to 11, on-chip RAM addresses H'FB80 to H'FD7F become inaccessible. 2. In devices with 2,048-byte RAM, if RLCT1 to 0 are set to any value except 00, these on-chip RAM addresses become inaccessible. 52 2.9 Application Notes 2.9.1 Notes on Data Access 1. The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. Data transfer from empty area to CPU: Unpredictable data is transferred. 2. Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register. Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. Figure 2-17 shows the data size and number of states in which on-chip peripheral modules can be accessed. 53 Access States Word Byte H'0000 H'0029 H'002A Interrupt vector area (42 bytes) 32 kbytes *2 On-chip ROM 2 H'7FFF*2 Reserved -- -- -- H'F740 LCD RAM *1 (64 bytes) H'F77F 2 Reserved -- -- -- H'FB80*3 On-chip RAM H'FF7F H'FF80 H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF H'FFA8 H'FFAD 32-byte serial data buffer x x x x 2 2 3 2 1,024 bytes*3 2 : Access possible x : Not possible Notes: The above example is a description of the H8/3834U. 1. The indicated addresses for the LCD RAM area are initial values after system reset. 2. The H8/3833U has 24 kbytes of on-chip ROM, and its ending address is H'5FFF. The H8/3835U has 40 kbytes of on-chip ROM, and its ending address is H'9FFF. The H8/3836U has 48 kbytes of on-chip ROM, and its ending address is H'BFFF. The H8/3837U has 60 kbytes of on-chip ROM, and its ending address is H'EDFF. 3. The H8/3833U has 1,024 bytes of on-chip RAM and its starting address is H'FB80. The H8/3835U, H8/3836U, and H8/3837U each have 2,048 bytes of on-chip RAM, and their starting address is H'F780. Figure 2-17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules 54 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O. Order of Operation 1 2 3 Read Modify Write Operation Read byte data at the designated address Modify a designated bit in the read data Write the altered byte data to the designated address 1. Bit manipulation in two registers assigned to the same address Example 1 Figure 2-18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. Order of Operation 1 2 3 Read Modify Write Operation Timer counter data is read (one byte) The CPU modifies (sets or resets) the bit designated in the instruction The altered byte data is written to the timer load register The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. R Count clock Timer counter R: Read W: Write W Timer load register Reload Internal bus Figure 2-18 Timer Configuration Example 55 Example 2 Here a BSET instruction is executed designating port 3. P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output. [A: Prior to executing BSET] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0 [B: BSET instruction executed] BSET #0 , @PDR3 The BSET instruction is executed designating port 3. [C: After executing BSET] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 0 P36 Input High level 0 1 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output High level 1 1 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3. Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input). P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of H'80, but the value read by the CPU is H'40. Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU writes this value (H'41) to PDR3, completing execution of BSET. 56 As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. B MOV. B MOV. B #80, R0L, R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 R0L @RAM0 @PDR3 P36 Input High level 0 0 0 The PDR3 value (H'80) is written to a work area in memory (RAM0) as well as to PDR3. P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output Low level 1 0 0 [B: BSET instruction executed] BSET #0 , @RAM0 The BSET instruction is executed designating the PDR3 work area (RAM0). 57 [C: After executing BSET] MOV. B MOV. B @RAM0, R0L R0L, @PDR3 P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 P36 Input High level 0 0 0 The work area (RAM0) value is written to PDR3. P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output High level 1 1 1 2. Bit manipulation in a register containing a write-only bit Example 3 In this example, the port 3 control register PCR3 is accessed by a BCLR instruction. As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is assumed that a high-level signal will be input to this input pin. [A: Prior to executing BCLR] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0 [B: BCLR instruction executed] BCLR #0 , @PCR3 The BCLR instruction is executed designating PCR3. 58 [C: After executing BCLR] P37 Input/output Pin state PCR3 PDR3 Output Low level 1 1 P36 Output High level 1 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Input High level 0 0 [D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR3 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR3 becomes 0, making P30 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins. To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] MOV. B MOV. B MOV. B #3F, R0L, R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 R0L @RAM0 @PCR3 P36 Input High level 0 0 0 The PCR3 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR3. P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output Low level 1 0 1 59 [B: BCLR instruction executed] BCLR #0 , @RAM0 The BCLR instruction is executed designating the PCR3 work area (RAM0). [C: After executing BCLR] MOV. B MOV. B @RAM0, R0L R0L, @PCR3 P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 P36 Input High level 0 0 0 The work area (RAM0) value is written to PCR3. P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output High level 0 0 0 The tables below list registers that share the same address, and registers that contain write-only bits. Registers with shared addresses Register Name Timer counter B and timer load register B Timer counter C and timer load register C Port data register 1* Port data register 2* Port data register 3* Port data register 4* Port data register 5* Port data register 6* Port data register 7* Port data register 8* Port data register 9* Port data register A* Abbreviation TCB/TLB TCC/TLC PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA Address H'FFB3 H'FFB5 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD Note: * These port registers are used also for pin input. 60 Registers with write-only bits Register Name Port control register 1 Port control register 2 Port control register 3 Port control register 4 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register 9 Port control register A Timer control register F PWM control register PWM data register U PWM data register L Abbreviation PCR1 PCR2 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA TCRF PWCR PWDRU PWDRL Address H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFED H'FFB6 H'FFD0 H'FFD1 H'FFD2 2.9.3 Notes on Use of the EEPMOV Instruction * The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L R6 + R4L * When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R6 R5 + R4L H'FFFF Not allowed R6 + R4L 61 Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3834U Series when a reset or interrupt occurs. Table 3-1 shows the priorities of these two types of exception handling. Table 3-1 Exception Handling Types and Priorities Priority High Exception Source Reset Interrupt Low Time of Start of Exception Handling Exception handling starts as soon as the reset state is cleared When an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 Reset 3.2.1 Overview A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized. 3.2.2 Reset Sequence As soon as the RES pin goes low, all processing is stopped and the H8/3834U enters the reset state. To make sure the chip is reset properly, observe the following precautions. * * At power on: Hold the RES pin low until the clock pulse generator output stabilizes. Resetting during operation: Hold the RES pin low for at least 10 system clock cycles. If the MD0 pin is at the high level, reset exception handling begins when the RES pin is held low for a given period, then returned to the high level. If the MD0 pin is low, however, when the RES pin is held low for a given period and then returned to high level, the reset is not cleared immediately. First the MD0 pin must go from low to high, then after 8,192 clock cycles the reset is cleared and reset exception handling begins. 63 Reset exception handling takes place as follows. * The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. * When system power is turned on or off, the RES pin should be held low. Figures 3-1 and 3-2 show the reset sequence. Reset cleared Program initial instruction prefetch Vector fetch Internal processing RES MD0 o High Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (1) (2) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3-1 Reset Sequence (when MD0 Pin is High) 64 Reset cleared Program initial instruction prefetch Vector fetch Internal processing RES MD0 o 8,192 clock cycles Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (2) (3) (1) (2) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3-2 Reset Sequence (when MD0 Pin is Low) 3.2.3 Interrupt Immediately after Reset After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP). 65 3.3 Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (WKP0 to WKP7, IRQ0 to IRQ4), and 20 internal interrupts from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features: * Both internal and external interrupts can be masked by the I bit of CCR. When this bit is set to 1, interrupt request flags are set but interrupts are not accepted. The external interrupt pins IRQ0 to IRQ4 can each be set independently to either rising edge sensing or falling edge sensing. * Table 3-2 Interrupt Sources and Priorities Priority High Interrupt Source RES IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Low SCI1 Interrupt Reset IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 SCI1 transfer complete 10 H'0014 to H'0015 Vector Number 0 4 5 6 7 8 9 Vector Address H'0000 to H'0001 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 66 Table 3-2 Interrupt Sources and Priorities (cont) Priority High Interrupt Source Timer A Timer B Timer C Timer FL Interrupt Timer A overflow Timer B overflow Timer C overflow or underflow Timer FL compare match Timer FL overflow Timer FH Timer FH compare match Timer FH overflow Timer G Timer G input capture Timer G overflow SCI2 SCI2 transfer complete SCI2 transfer abort SCI3 SCI3 transmit end SCI3 transmit data empty SCI3 receive data full SCI3 overrun error SCI3 framing error SCI3 parity error A/D converter Low (SLEEP instruction executed) A/D conversion end Direct transfer 19 20 H'0026 to H'0027 H'0028 to H'0029 18 H'0024 to H'0025 17 H'0022 to H'0023 16 H'0020 to H'0021 15 H'001E to H'001F Vector Number 11 12 13 14 Vector Address H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D Note: Vector addresses H'0002 to H'0007 are reserved and cannot be used. 67 3.3.2 Interrupt Control Registers Table 3-3 lists the registers that control interrupts. Table 3-3 Interrupt Control Registers Register Name IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 1 Interrupt request register 2 Wakeup interrupt request register Abbreviation IEGR IENR1 IENR2 IRR1 IRR2 IWPR R/W R/W R/W R/W R/W* R/W* R/W* Initial Value H'E0 H'00 H'00 H'20 H'00 H'00 Address H'FFF2 H'FFF3 H'FFF4 H'FFF6 H'FFF7 H'FFF9 Note: * Write is enabled only for writing of 0 to clear a flag. 1. Bit IRQ edge select register (IEGR) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 IEG4 0 R/W 3 IEG3 0 R/W 2 IEG2 0 R/W 1 IEG1 0 R/W 0 IEG0 0 R/W Initial value Read/Write IEGR is an 8-bit read/write register, used to designate whether pins IRQ0 to IRQ4 are set to rising edge sensing or falling edge sensing. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: IRQ4 edge select (IEG4) Bit 4 selects the input sensing of pin IRQ4/ADTRG. Bit 4 IEG4 0 1 Description Falling edge of IRQ4/ADTRG pin input is detected Rising edge of IRQ4/ADTRG pin input is detected (initial value) 68 Bit 3: IRQ3 edge select (IEG3) Bit 3 selects the input sensing of pin IRQ3/TMIF. Bit 3 IEG3 0 1 Description Falling edge of IRQ3/TMIF pin input is detected Rising edge of IRQ3/TMIF pin input is detected (initial value) Bit 2: IRQ2 edge select (IEG2) Bit 2 selects the input sensing of pin IRQ2/TMIC. Bit 2 IEG2 0 1 Description Falling edge of IRQ2/TMIC pin input is detected Rising edge of IRQ2/TMIC pin input is detected (initial value) Bit 1: IRQ1 edge select (IEG1) Bit 1 selects the input sensing of pin IRQ1/TMIB. Bit 1 IEG1 0 1 Description Falling edge of IRQ1/TMIB pin input is detected Rising edge of IRQ1/TMIB pin input is detected (initial value) Bit 0: IRQ0 edge select (IEG0) Bit 0 selects the input sensing of pin IRQ0. Bit 0 IEG0 0 1 Description Falling edge of IRQ0 pin input is detected Rising edge of IRQ0 pin input is detected (initial value) 69 2. Bit Interrupt enable register 1 (IENR1) 7 IENTA 0 R/W 6 IENS1 0 R/W 5 IENWP 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W 2 IEN2 0 R/W 1 IEN1 0 R/W 0 IEN0 0 R/W Initial value Read/Write IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests. Bit 7 IENTA 0 1 Description Disables timer A interrupts Enables timer A interrupts (initial value) Bit 6: SCI1 interrupt enable (IENS1) Bit 6 enables or disables SCI1 transfer complete interrupt requests. Bit 6 IENS1 0 1 Description Disables SCI1 interrupts Enables SCI1 interrupts (initial value) Bit 5: Wakeup interrupt enable (IENWP) Bit 5 enables or disables WKP7 to WKP0 interrupt requests. Bit 5 IENWP 0 1 Description Disables interrupt requests from WKP7 to WKP0 Enables interrupt requests from WKP7 to WKP0 (initial value) 70 Bits 4 to 0: IRQ4 to IRQ0 interrupt enable (IEN4 to IEN0) Bits 4 to 0 enable or disable IRQ4 to IRQ0 interrupt requests. Bit n IENn 0 1 Description Disables interrupt request IRQn Enables interrupt request IRQn (n = 4 to 0) (initial value) 3. Bit Interrupt Enable Register 2 (IENR2) 7 IENDT 0 R/W 6 IENAD 0 R/W 5 IENS2 0 R/W 4 IENTG 0 R/W 3 0 R/W 2 0 R/W 1 IENTC 0 R/W 0 IENTB 0 R/W IENTFH IENTFL Initial value Read/Write IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Direct transfer interrupt enable (IENDT) Bit 7 enables or disables direct transfer interrupt requests. Bit 7 IENDT 0 1 Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value) Bit 6: A/D converter interrupt enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD 0 1 Description Disables A/D converter interrupt requests Enables A/D converter interrupt requests (initial value) 71 Bit 5: SCI2 interrupt enable (IENS2) Bit 5 enables or disables SCI2 transfer complete and transfer abort interrupt requests. Bit 5 IENS2 0 1 Description Disables SCI2 interrupts Enables SCI2 interrupts (initial value) Bit 4: Timer G interrupt enable (IENTG) Bit 4 enables or disables timer G input capture and overflow interrupt requests. Bit 4 IENTG 0 1 Description Disables timer G interrupts Enables timer G interrupts (initial value) Bit 3: Timer FH interrupt enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests. Bit 3 IENTFH 0 1 Description Disables timer FH interrupts Enables timer FH interrupts (initial value) Bit 2: Timer FL interrupt enable (IENTFL) Bit 2 enables or disables timer FL compare match and overflow interrupt requests. Bit 2 IENTFL 0 1 Description Disables timer FL interrupts Enables timer FL interrupts (initial value) 72 Bit 1: Timer C interrupt enable (IENTC) Bit 1 enables or disables timer C overflow or underflow interrupt requests. Bit 1 IENTC 0 1 Description Disables timer C interrupts Enables timer C interrupts (initial value) Bit 0: Timer B interrupt enable (IENTB) Bit 0 enables or disables timer B overflow or underflow interrupt requests. Bit 0 IENTB 0 1 Description Disables timer B interrupts Enables timer B interrupts (initial value) SCI3 interrupt control is covered in 10.4.2, in the description of serial control register 3. 4. Bit Initial value Read/Write Interrupt request register 1 (IRR1) 7 IRRTA 0 R/W* 6 IRRS1 0 R/W* 5 -- 1 -- 4 IRRI4 0 R/W* 3 IRRI3 0 R/W* 2 IRRI2 0 R/W* 1 IRRI1 0 R/W* 0 IRRI0 0 R/W* Note: * Only a write of 0 for flag clearing is possible. IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A, SCI1, or IRQ4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7: Timer A interrupt request flag (IRRTA) Bit 7 IRRTA 0 1 Description Clearing conditions: When IRRTA = 1, it is cleared by writing 0 Setting conditions: When the timer A counter value overflows (goes from H'FF to H'00) (initial value) 73 Bit 6: SCI1 interrupt request flag (IRRS1) Bit 6 IRRS1 0 1 Description Clearing conditions: When IRRS1 = 1, it is cleared by writing 0 Setting conditions: When an SCI1 transfer is completed (initial value) Bit 5: Reserved bit Bit 5 is reserved; it is always read as 1, and cannot be modified. Bits 4 to 0: IRQ4 to IRQ0 interrupt request flags (IRRI4 to IRRI0) Bit n IRRIn 0 1 Description Clearing conditions: When IRRIn = 1, it is cleared by writing 0 to IRRIn. (initial value) Setting conditions: IRRIn is set when pin IRQn is set to interrupt input, and the designated signal edge is detected. (n = 4 to 0) 5. Bit Interrupt request register 2 (IRR2) 7 IRRDT 0 R/W * 6 IRRAD 0 R/W * 5 IRRS2 0 R/W * 4 IRRTG 0 R/W * 3 0 R/W * 2 0 R/W * 1 IRRTC 0 R/W * 0 IRRTB 0 R/W * IRRTFH IRRTFL Initial value Read/Write Note: * Only a write of 0 for flag clearing is possible. IRR2 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a direct transfer, A/D converter, SCI2, timer G, timer FH, timer FL, timer C, or timer B interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. 74 Bit 7: Direct transfer interrupt request flag (IRRDT) Bit 7 IRRDT 0 1 Description Clearing conditions: When IRRDT = 1, it is cleared by writing 0 (initial value) Setting conditions: When DTON = 1 and a direct transfer is made immediately after a SLEEP instruction is executed Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6 IRRAD 0 1 Description Clearing conditions: When IRRAD = 1, it is cleared by writing 0 Setting conditions: When A/D conversion is completed and ADSF is reset (initial value) Bit 5: SCI2 interrupt request flag (IRRS2) Bit 5 IRRS2 0 1 Description Clearing conditions: When IRRS2 = 1, it is cleared by writing 0 Setting conditions: When an SCI2 transfer is completed or aborted (initial value) Bit 4: Timer G interrupt request flag (IRRTG) Bit 4 IRRTG 0 1 Description Clearing conditions: When IRRTG = 1, it is cleared by writing 0 (initial value) Setting conditions: When pin TMIG is set to TMIG input and the designated signal edge is detected 75 Bit 3: Timer FH interrupt request flag (IRRTFH) Bit 3 IRRTFH 0 1 Description Clearing conditions: When IRRTFH = 1, it is cleared by writing 0 (initial value) Setting conditions: When counter FH matches output compare register FH in 8-bit timer mode, or when 16-bit counter F (TCFL, TCFH) matches output compare register F (OCRFL, OCRFH) in 16-bit timer mode Bit 2: Timer FL interrupt request flag (IRRTFL) Bit 2 IRRTFL 0 1 Description Clearing conditions: When IRRTFL = 1, it is cleared by writing 0 (initial value) Setting conditions: When counter FL matches output compare register FL in 8-bit timer mode Bit 1: Timer C interrupt request flag (IRRTC) Bit 1 IRRTC 0 1 Description Clearing conditions: When IRRTC = 1, it is cleared by writing 0 (initial value) Setting conditions: When the timer C counter value overflows (goes from H'FF to H'00) or underflows (goes from H'00 to H'FF) Bit 0: Timer B interrupt request flag (IRRTB) Bit 0 IRRTB 0 1 Description Clearing conditions: When IRRTB = 1, it is cleared by writing 0 Setting conditions: When the timer B counter value overflows (goes from H'FF to H'00) (initial value) 76 6. Bit Wakeup interrupt request register (IWPR) 7 IWPF7 0 R/W * 6 IWPF6 0 R/W * 5 IWPF5 0 R/W * 4 IWPF4 0 R/W * 3 IWPF3 0 R/W * 2 IWPF2 0 R/W * 1 IWPF1 0 R/W * 0 IWPF0 0 R/W * Initial value Read/Write Note: * Only a write of 0 for flag clearing is possible. IWPR is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins WKP7 to WKP0 are set to wakeup input and a pin receives a falling edge input. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bits 7 to 0: Wakeup interrupt request flags (WKPF7 to WKPF0) Bit n IWPFn 0 1 Description Clearing conditions: When IWPFn = 1, it is cleared by writing 0 to IWPFn. Setting conditions: IWPFn is set when pin WKPn is set to wakeup interrupt input, and a falling edge input is detected at the pin. (n = 7 to 0) 3.3.3 External Interrupts There are 13 external interrupts, WKP0 to WKP7 and IRQ0 to IRQ4. 1. Interrupts WKP0 to WKP7 Interrupts WKP0 to WKP7 are requested by falling edge inputs at pins WKP0 to WKP7. When these pins are designated as WKP0 to WKP7 pins in port mode register 5 (PMR5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request register (IWPR) is set to 1, requesting an interrupt. Wakeup interrupt requests can be disabled by clearing the IENWP bit in IENR1 to 0. It is also possible to mask all interrupts by setting the CCR I bit to 1. When an interrupt exception handling request is received for interrupts WKP0 to WKP7, the CCR I bit is set to 1. The vector number for interrupts WKP0 to WKP7 is 9. Since all eight interrupts are assigned the same vector number, the interrupt source must be determined by the exception handling routine. 77 2. Interrupts IRQ0 to IRQ4 Interrupts IRQ0 to IRQ4 are requested by into pins inputs to IRQ0 to IRQ4. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR). When these pins are designated as pins IRQ0 to IRQ4 in port mode registers 1 and 2 (PMR1 and PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Interrupts IRQ0 to IRQ4 can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When IRQ0 to IRQ4 interrupt exception handling is initiated, the I bit is set to 1. Vector numbers 4 to 8 are assigned to interrupts IRQ0 to IRQ4. The order of priority is from IRQ0 (high) to IRQ4 (low). Table 3-2 gives details. 3.3.4 Internal Interrupts There are 20 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt request is accepted, the I bit is set to 1. Vector numbers 10 to 20 are assigned to these interrupts. Table 3-2 shows the order of priority of interrupts from on-chip peripheral modules. 78 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-3 shows a block diagram of the interrupt controller. Figure 3-4 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Priority decision logic Interrupt request External interrupts or internal interrupt enable signals I CCR (CPU) Figure 3-3 Block Diagram of Interrupt Controller Interrupt operation is described as follows. * When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. When the interrupt controller receives an interrupt request, it sets the interrupt request flag. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3-2 for a list of interrupt priorities.) * * 79 * The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-5. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. The I bit of CCR is set to 1, masking all further interrupts. The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. * * * Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (I = 1). If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. 2. 80 Program execution state IRRIO = 1 Yes IENO = 1 Yes No No No IRRI1 = 1 Yes IEN1 = 1 Yes No No IRRI2 = 1 Yes IEN2 = 1 Yes No IRRDT = 1 Yes IENDT = 1 Yes No No No I=0 Yes PC contents saved CCR contents saved I1 Branch to interrupt handling routine Notation: PC: Program counter CCR: Condition code register I: I bit of CCR Figure 3-4 Flow up to Interrupt Acceptance 81 SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area SP (R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR* PCH PCL Even address Prior to start of interrupt exception handling Notation: PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer PC and CCR saved to stack After completion of interrupt exception handling Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word access, starting from an even-numbered address. * Ignored on return from interrupt. Figure 3-5 Stack State after Completion of Interrupt Exception Handling Figure 3-6 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. 82 Interrupt is accepted Interrupt level decision and wait for end of instruction Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction of Internal interrupt-handling routine processing Interrupt request signal o Internal address bus (1) (3) (5) (6) (8) (9) Figure 3-6 Interrupt Sequence (2) (4) (1) (7) (9) 83 Internal read signal Internal write signal (10) Internal data bus (16 bits) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine 3.3.6 Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Total Note: * Not including EEPMOV instruction. States 1 to 13 4 2 4 4 15 to 27 84 3.4 Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3834U Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-7. SP SP PCH PC L SP R1L PC L H'FEFC H'FEFD H'FEFF BSR instruction SP set to H'FEFF MOV. B R1L, @-R7 Contents of PCH are lost Stack accessed beyond SP Notation: PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer Figure 3-7 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored. 85 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls these pins (IRQ4 to IRQ0, and WKP7 to WKP0), the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching pin functions. Table 3-5 shows the conditions under which interrupt request flags are set to 1 in this way. Table 3-5 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 IRR1 IRRI4 Conditions * When PMR2 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit IEG4 = 0. * When PMR2 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit IEG4 = 1. IRRI3 * When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit IEG3 = 0. * When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit IEG3 = 1. IRRI2 * When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR bit IEG2 = 0. * When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR bit IEG2 = 1. IRRI1 * When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 = 0. * When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 = 1. IRRI0 * When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR bit IEG0 = 0. * When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR bit IEG0 = 1. 86 Table 3-5 Conditions under which Interrupt Request Flag is Set to 1 (cont) Interrupt Request Flags Set to 1 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Conditions When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low Figure 3-8 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3-5 do not occur. Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) CCR I bit 1 Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 CCR I bit 0 Interrupt mask cleared Figure 3-8 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure 87 Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 Block Diagram Figure 4-1 shows a block diagram of the clock pulse generators. OSC 1 OSC 2 System clock oscillator o OSC (f OSC) oOSC/2 System clock divider (1/2) System clock oOSC/16 divider (1/8) o Prescaler S (13 bits) oW /2 oW /4 oW /8 o/2 to o/8192 oW oSUB oW /2 oW /4 oW /8 to oW /128 System clock pulse generator X1 X2 Subclock oscillator oW Subclock divider (f W ) (1/2, 1/4, 1/8) Subclock pulse generator Prescaler W (5 bits) Figure 4-1 Block Diagram of Clock Pulse Generators 4.1.2 System Clock and Subclock The basic clock signals that drive the CPU and on-chip peripheral modules are o and oSUB. Four of the clock signals have names: o is the system clock, oSUB is the subclock, oOSC is the oscillator clock, and oW is the watch clock. The clock signals available for use by peripheral modules are o/2, o/4, o/8, o/16, o/32, o/64, o/128, o/256, o/512, o/1024, o/2048, o/4096, o/8192, oW, oW/2, oW/4, oW/8, oW/16, oW/32, oW/64, and oW/128. The clock requirements differ from one module to another. 89 4.2 System Clock Generator Clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. Connecting a crystal oscillator Figure 4-2 shows a typical method of connecting a crystal oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = C 2 = 12 pF 20% Figure 4-2 Typical Connection to Crystal Oscillator Figure 4-3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 4-1 should be used. CS LS OSC 1 RS OSC 2 C0 Figure 4-3 Equivalent Circuit of Crystal Oscillator Table 4-1 Crystal Oscillator Parameters Frequency (MHz) Rs max () Co max (pF) 2 500 7 4 100 8 50 10 30 90 2. Connecting a ceramic oscillator Figure 4-4 shows a typical method of connecting a ceramic oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = 30 pF 10% C2 = 30 pF 10% Ceramic oscillator: Murata Figure 4-4 Typical Connection to Ceramic Oscillator 3. Notes on board design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4-5.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2. To be avoided Signal A Signal B C2 OSC 1 OSC 2 C1 Figure 4-5 Board Design of Oscillator Circuit 91 4. External clock input method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4-6 shows a typical connection. OSC 1 OSC 2 External clock input Open Figure 4-6 External Clock Input (Example) Frequency Duty cycle Oscillator Clock (oOSC) 45% to 55% 92 4.3 Subclock Generator 1. Connecting a 32.768-kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted under 4.2.3 for the system clock. C1 X1 X2 C2 C1 = C 2 = 15 pF (typ.) Figure 4-7 Typical Connection to 32.768-kHz Crystal Oscillator (Subclock) Figure 4-8 shows the equivalent circuit of the 32.768-kHz crystal oscillator. CS LS X1 RS X2 C0 C0 = 1.5 pF typ RS = 14 k typ f W = 32.768 kHz Crystal oscillator: MX38T (Nihon Denpa Kogyo) Figure 4-8 Equivalent Circuit of 32.768-kHz Crystal Oscillator 93 2. Inputting an external clock (1) Circuit configuration An external clock is input to the X1 pin. The X2 pin should be left open. An example of the connection in this case is shown in figure 4-9. External clock input X1 X2 Open Figure 4-9 Example of Connection when Inputting an External Clock (2) External clock Input a square waveform to the X1 pin. When using the CPU, timer A, timer C, timer G, or an LCD, with a subclock (ow) clock selected, do not stop the clock supply to the X1 pin. txH VIH VIL txr txf txL Figure 4-10 External Subclock Timing The DC characteristics and timing of an external clock input to the X1 pin are shown in table 4-2. 94 Table 4-2 DC Characteristics and Timing (VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified, including subactive mode) Applicable Pin X1 Test Conditions Values Min VCC -0.3 -0.3 -- -- -- 12.0 12.0 Typ -- -- -- -- 32.768 -- -- Max VCC +0.3 0.3 100 100 -- -- -- kHz s s Figure 4.10 ns Figure 4.10 Unit V Notes Figure 4.10 Item Input high voltage Input low voltage External subclock rise time External subclock fall time Symbol VIH VIL txr txf External subclock fx oscillation frequency External subclock high width External subclock low width txH txL 3. Pin connection when not using subclock When the subclock is not used, connect pin X1 to VCC and leave pin X2 open, as shown in figure 4-11. VCC X1 X2 Open Figure 4-11 Pin Connection when not Using Subclock 95 4.4 Prescalers The H8/3834U Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (o) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 (oW/4) as its input clock. Its prescaled outputs are used by timer A as a time base for timekeeping. 1. Prescaler S (PSS) Prescaler S is a 13-bit counter using the system clock (o) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by timer A, timer B, timer C, timer F, timer G, SCI1, SCI2, SCI3, the A/D converter, LCD controller, and 14-bit PWM. The divider ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode the clock input to prescaler S is oOSC/16. 2. Prescaler W (PSW) Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (oW/4) as its input clock. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base for timekeeping. 96 4.5 Note on Oscillators Oscillator characteristics of both the masked ROM and ZTATTM versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. 97 Section 5 Power-Down Modes 5.1 Overview The H8/3834U Series has seven modes of operation after a reset. These include six power-down modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the seven operation modes. All but the active (high-speed) mode are power-down modes. Table 5-1 Operation Modes Operating Mode Active (high-speed) mode Active (medium-speed) mode Subactive mode Sleep mode Subsleep mode Watch mode Standby mode Description The CPU runs on the system clock, executing program instructions at high speed The CPU runs on the system clock, executing program instructions at reduced speed The CPU runs on the subclock, executing program instructions at reduced speed The CPU halts. On-chip peripheral modules continue to operate on the system clock. The CPU halts. Timer A, timer C, timer G, and the LCD controller/driver continue to operate on the subclock. The CPU halts. The time-base function of timer A and the LCD controller/driver continue to operate on the subclock. The CPU and all on-chip peripheral modules stop operating In this section the two active modes (high-speed and medium-speed) are referred to collectively as active mode. 99 Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal states in each mode. Program execution state Reset state LSON = 0, MSON = 0 Program halt state n in st ru ct io Program halt state Active (high-speed) mode *1 P ion EE uct SL str in SL in SL n EE P st ru ct io LSON = 0, MSON = 1 Active (medium-speed) mode D TO *4 *1 SSBY = 1, TMA3 = 1 D N TO = 1 Watch mode P EE SL in ti uc str on = 1 D N TO in st ru P N *3 ct io EE EE P = n Standby mode SL in st ru ct io n SSBY = 1, TMA3 = 0, LSON = 0 P EE *4 *3 SSBY = 0, LSON = 0 SL 1 Sleep mode SL *1 EE P in st ru LSON = 1, TMA3 = 1 ct io n SLEEP instruction *2 SSBY = 0, LSON = 1, TMA3 = 1 Subactive mode Subsleep mode : Transition caused by exception handling Power-down mode A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that the interrupt is accepted and interrupt handling is performed. Details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 through 5.8. Notes: 1. Timer A interrupt, IRQ 0 interrupt, WKP0 to WKP7 interrupts 2. Timer A interrupt, timer C interrupt, timer G interrupt, IRQ 0 to IRQ 4 interrupts, WKP0 to WKP7 interrupts 3. All interrupts 4. IRQ 0 interrupt, IRQ 1 interrupt, WKP0 to WKP7 interrupts Figure 5-1 Operation Mode Transition Diagram 100 Table 5-2 Internal State in Each Operation Mode Active Mode Function Subclock oscillator High Speed Functions Medium Speed Functions Functions Functions Sleep Mode Functions Functions Halted Retained Watch Mode Halted Functions Halted Retained Subactive Subsleep Mode Mode Halted Functions Functions Halted Functions Halted Retained Standby Mode Halted Functions Halted Retained Retained*1 Functions Functions Functions Functions Retained*6 Retained*6 Functions Functions Functions System clock oscillator Functions CPU Instructions Functions operation RAM Registers I/O External IRQ0 interrupts IRQ 1 IRQ2 IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Peripheral Timer A module Timer B functions Timer C Timer F Timer G SCI1 SCI2 SCI3 PWM A/D LCD Notes: 1. 2. 3. 4. 5. 6. Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions*5 Functions*5 Functions*5 Retained Retained Retained Retained Functions/ Functions/ Retained*2 Retained*2 Retained Retained Functions/ Functions/ Retained*3 Retained*3 Functions Functions Retained Reset Retained Reset Retained Retained Retained Reset Retained Retained Retained Reset Retained Retained Functions Functions Functions Retained Functions Functions Retained Retained Functions/ Functions/ Functions/ Retained Retained*4 Retained*4 Retained*4 Register contents held; high-impedance output. Functions only if external clock or oW/4 internal clock is selected; otherwise halted and retained. Functions only if oW/2 internal clock is selected; otherwise halted and retained. Functions only if oW or oW/2 internal clock is selected; otherwise halted and retained. Functions when timekeeping time-base function is selected. External interrupt requests are ignored. The interrupt request register contents are not affected. 101 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5-3. Table 5-3 System Control Register Name System control register 1 System control register 2 Abbreviation SYSCR1 SYSCR2 R/W R/W R/W Initial Value H'07 H'E0 Address H'FFF0 H'FFF1 1. Bit System control register 1 (SYSCR1) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value Read/Write SYSCR1 is an 8-bit read/write register for control of the power-down modes. Bit 7: Software standby (SSBY) This bit designates transition to standby mode or watch mode. Bit 7 SSBY 0 Description * When a SLEEP instruction is executed in active mode, a transition is made to sleep mode. (initial value) * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode. 1 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode. * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode. Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 10 ms. 102 Bit 6 STS2 0 0 0 0 1 Bit 5 STS1 0 0 1 1 * Bit 4 STS0 0 1 0 1 * Description Wait time = 8,192 states Wait time = 16,384 states Wait time = 32,768 states Wait time = 65,536 states Wait time = 131,072 states (initial value) Note: * Don't care Bit 3: Low speed on flag (LSON) This bit chooses the system clock (o) or subclock (oSUB) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3 LSON 0 1 Description The CPU operates on the system clock (o) The CPU operates on the subclock (oSUB) (initial value) Bits 2 to 0: Reserved bits These bits are reserved; they are always read as 1, and cannot be modified. 2. Bit Initial value Read/Write System control register 2 (SYSCR2) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 NESEL 0 R/W 3 DTON 0 R/W 2 MSON 0 R/W 1 SA1 0 R/W 0 SA0 0 R/W SYSCR2 is an 8-bit read/write register for power-down mode control. Bits 7 to 5: Reserved bits These bits are reserved; they are always read as 1, and cannot be modified. Bit 4: Noise elimination sampling frequency select (NESEL) This bit selects the frequency at which the watch clock signal (oW) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (oOSC) generated by the system clock pulse generator. When oOSC = 2 to 10 MHz, clear NESEL to 0. 103 Bit 4 NESEL 0 1 Description Sampling rate is oOSC/16 Sampling rate is oOSC/4 Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits. Bit 3 DTON 0 Description When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. (initial value) When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. 1 When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1. Bit 2: Medium speed on flag (MSON) After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. Bit 2 MSON 0 1 Description Operation is in active (high-speed) mode Operation is in active (medium-speed) mode (initial value) 104 Bits 1 and 0: Subactive mode clock select (SA1 and SA0) These bits select the CPU clock rate (oW/2, oW/4, or oW/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 SA1 0 0 1 Bit 0 SA0 0 1 * Description oW/8 oW/4 oW/2 (initial value) Note: * Don't care 5.2 Sleep Mode 5.2.1 Transition to Sleep Mode The system goes from active mode to sleep mode when a SLEEP instruction is executed while the SSBY and LSON bits in system control register 1 (SYSCR1) are cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral functions other than PWM are operational. The CPU register contents are retained. 5.2.2 Clearing Sleep Mode Sleep mode is cleared by an interrupt (timer A, timer B, timer C, timer F, timer G, IRQ0 to IRQ4, WKP0 to WKP7, SCI1, SCI2, SCI3, A/D converter) or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (mediumspeed) mode if MSON = 1. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 105 5.3 Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. As long as a minimum required voltage is applied, the CPU register contents and data in the on-chip RAM will be retained. The I/O ports go to the high-impedance state. 5.3.2 Clearing Standby Mode Standby mode is cleared by an interrupt (IRQ0, IRQ1, WKP0 to WKP7) or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2-STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input When the RES pin goes low, the system clock pulse generator starts and standby mode is cleared. After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin should be kept at the low level until the pulse generator output stabilizes. 5.3.3 Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. * When a crystal oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time of at least 10 ms. 106 * When an external clock is used Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set. Table 5-3 Clock Frequency and Settling Time (times are in ms) STS2 0 0 0 0 1 STS1 0 0 1 1 * STS0 0 1 0 1 * Waiting Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 5 MHz 1.6 3.2 6.6 13.1 26.2 4 MHz 2.0 4.1 8.2 16.4 32.8 2 MHz 4.1 8.2 16.4 32.8 65.5 1 MHz 8.2 16.4 32.8 65.5 131.1 0.5 MHz 16.4 32.8 65.5 131.1 262.1 Note: * Don't care 5.3.4 Transition to Standby Mode and Port Pin States The system goes from active (high-speed or medium-speed) mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in TMA is cleared to 0. Port pins (except those with their MOS pull-up turned on) enter high-impedance state when the transition to standby mode is made. This timing is shown in figure 5-2. Internal data bus SLEEP instruction fetch Next instruction fetch SLEEP instruction execution Internal processing Port pins Output Active (high-speed or medium-speed) mode High-impedance Standby mode Figure 5-2 Transition to Standby Mode and Port Pin States 107 5.4 Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules other than timer A and the LCD controller is halted. The LCD controller can be selected to operate or to halt. As long as a minimum required voltage is applied, the contents of CPU registers and some registers of the onchip peripheral modules, and the on-chip RAM contents, are retained. I/O ports keep the same states as before the transition. 5.4.2 Clearing Watch Mode Watch mode is cleared by an interrupt (timer A, IRQ0, WKP0 to WKP7) or by a low input at the RES pin. * Clearing by interrupt Watch mode is cleared when an interrupt is requested. The mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 5.4.3 Oscillator Settling Time after Watch Mode is Cleared The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after Standby Mode is Cleared. 108 5.5 Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than timer A, timer C, timer G, and the LCD controller is halted. As long as a minimum required voltage is applied, the contents of CPU registers and some registers of the on-chip peripheral modules, and the on-chip RAM contents, are retained. I/O ports keep the same states as before the transition. 5.5.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, timer C, timer G, IRQ0 to IRQ4, WKP0 to WKP7) or by a low input at the RES pin. * Clearing by interrupt When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 109 5.6 Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, IRQ0, or WKP0 to WKP7 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer G, IRQ0 to IRQ4, or WKP0 to WKP7 interrupt is requested. A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 Clearing Subactive Mode Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin. * Clearing by SLEEP instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer, below. * Clearing by RES pin Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 5.6.3 Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are oW/2, oW/4, and oW/8. 110 5.7 Active (medium-speed) Mode 5.7.1 Transition to Active (medium-speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0, IRQ1, or WKP0 to WKP7 interrupts in standby mode, timer A, IRQ0, or WKP0 to WKP7 interrupts in watch mode, or any interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 Clearing Active (medium-speed) Mode Active (medium-speed) mode is cleared by a SLEEP instruction or by a low input at the RES pin. * Clearing by SLEEP instruction A transition to standby mode takes place if a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1 when a SLEEP instruction is executed. Sleep mode is entered if both SSBY and LSON are cleared to 0 when a SLEEP instruction is executed. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See 5.8, Direct Transfer, below for details. * Clearing by RES pin When the RES pin goes low, the CPU enters the reset state and active (medium-speed) mode is cleared. 5.7.3 Operating Frequency in Active (medium-speed) Mode In active (medium-speed) mode, the CPU is clocked at 1/8 the frequency in active (high-speed) mode. 111 5.8 Direct Transfer 5.8.1 Direct Transfer Overview The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts. If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. * Direct transfer from active (high-speed) mode to active (medium-speed) mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. * Direct transfer from active (medium-speed) mode to active (high-speed) mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. * Direct transfer from active (high-speed) mode to subactive mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (high-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. 112 * Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. 5.8.2 Calculation of Direct Transfer Time before Transition * Time required before direct transfer from active (high-speed) mode to active (medium-speed) mode A direct transfer is made from active (high-speed) mode to active (medium-speed) mode when a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt exception handling completion is calculated by expression (1) below. Direct transfer time = (number of states for SLEEP instruction execution + number of states for internal processing) x tcyc before transition + number of states for interrupt exception handling execution x tcyc after transition ...... (1) Example: Direct transfer time for the H8/3834U Series = (2 + 1) x 2tosc + 14 x 16tosc = 230 tosc Notation: tosc: OSC clock cycle time tcyc: System clock () cycle time * Time required before direct transfer from active (medium-speed) mode to active (high-speed) mode A direct transfer is made from active (medium-speed) mode to active (high-speed) mode when a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt exception handling completion is calculated by expression (2) below. 113 Direct transfer time = (number of states for SLEEP instruction execution + number of states for internal processing) x tcyc before transition + number of states for interrupt exception handling execution x tcyc after transition ...... (2) Example: Direct transfer time for the H8/3834U Series = (2 + 1) x 16tosc + 14 x 2tosc = 76 tosc Notation: tosc: OSC clock cycle time tcyc: System clock () cycle time * Time required before direct transfer from subactive mode to active (high-speed) mode A direct transfer is made from subactive mode to active (high-speed) mode when a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt exception handling completion is calculated by expression (3) below. Direct transfer time = (number of states for SLEEP instruction execution + number of states for internal processing) x tsubcyc before transition + (wait time designated by STS2 to STS0 bits in SCR + number of states for interrupt exception handling execution) x tcyc after transition ...... (3) Example: Direct transfer time for the H8/3834U Series (when CPU clock frequency is w/8 and wait time is 8192 states) = (2 + 1) x 8tw + (8192 + 14) x 2tosc = 24tw + 16412tosc Notation: tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock () cycle time tsubcyc: Subclock (SUB) cycle time * Time required before direct transfer from subactive mode to active (medium-speed) mode A direct transfer is made from subactive mode to active (medium-speed) mode when a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON and DTON bits in SYSCR2 are set to 1, and the TMA3 bit in TMA is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt exception handling completion is calculated by expression (4) below. Direct transfer time = (number of states for SLEEP instruction execution + number of states for internal processing) x tsubcyc before transition + (wait time designated by 114 STS2 to STS0 bits in SCR + number of states for interrupt exception handling execution) x tcyc after transition ...... (4) Example: Direct transfer time for the H8/3834U Series (when CPU clock frequency is w/8 and wait time is 8192 states) = (2 + 1) x 8tw + (8192 + 14) x 16tosc = 24tw + 131296tosc Notation: tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock () cycle time tsubcyc: Subclock (SUB) cycle time 115 Section 6 ROM 6.1 Overview The H8/3833U has 24 kbytes of on-chip ROM, while the H8/3834U has 32 kbytes, the H8/3835U has 40 kbytes, the H8/3836U has 48 kbytes, and the H8/3837U has 60 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. The ZTATTM versions of the H8/3834U and H8/3837U each have 32 kbytes and 60 kbytes of PROM. 6.1.1 Block Diagram Figure 6-1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0000 H'0002 H'0001 H'0003 On-chip ROM H'7FFE H'7FFE Even-numbered address H'7FFF Odd-numbered address Figure 6-1 ROM Block Diagram (H8/3834U) 117 6.2 H8/3834U PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C256 EPROM. Table 6-1 shows how to set the chip to PROM mode. Table 6-1 Setting to PROM Mode Pin Name TEST PB4/AN4 PB5/AN5 PB6/AN6 High level Setting High level Low level 6.2.2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM. A socket adapter is required for conversion to 28 pins, as listed in table 6-2. Figure 6-2 shows the pin-to-pin wiring of the socket adapter. Figure 6-3 shows a memory map. Table 6-2 Socket Adapter Package 100-pin (FP-100B) 100-pin (FP-100A) 100-pin (TFP-100B) Socket Adapter HS3834ESH01H HS3834ESF01H HS3834ESN01H 118 H8/3834U FP-100A 12 47 48 49 50 51 52 53 54 70 69 68 67 66 65 64 63 55 91 57 58 59 60 61 62 56 34, 79 92 6 8 99 13 81 82 83 9, 30 5 97 98 84 85 86 FP-100B 9 44 45 46 47 48 49 50 51 67 66 65 64 63 62 61 60 52 88 54 55 56 57 58 59 53 31, 76 89 3 5 96 10 78 79 80 6, 27 2 94 95 81 82 83 Pin RES P60 P61 P62 P63 P64 P65 P66 P67 P87 P86 P85 P84 P83 P82 P81 P80 P70 P43 P72 P73 P74 P75 P76 P77 P71 VCC AVCC TEST X1 PB6 MD0 P11 P12 P13 VSS AVSS PB4 PB5 P14 P15 P16 EPROM socket Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 CE OE VCC HN27C256 1 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 VSS 14 Note: Pins not indicated in the figure should be left open. Figure 6-2 Socket Adapter Pin Correspondence (with HN27C256) 119 Address in MCU mode H'0000 Address in PROM mode H'0000 On-chip PROM H'7FFF H'7FFF Figure 6-3 H8/3834U Memory Map in PROM Mode Note: When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF. 120 6.3 H8/3834U Programming The write, verify, and other modes are selected as shown in table 6-3 in H8/3834U PROM mode. Table 6-3 Mode Selection in H8/3834U PROM Mode Pin Mode Write Verify Programming disabled Notation: L: Low level H: High level VPP: VPP level VCC: VCC level CE L H H OE H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA14 to EA0 Address input Address input Address input The specifications for writing and reading the on-chip PROM are identical to those for the standard HN27C256 EPROM. 6.3.1 Writing and Verifying An efficient, high-performance programming method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. H'FF data is written in unused address areas. The basic flow of this high-performance programming method is shown in figure 6-4. Table 6-4 and table 6-5 give the electrical characteristics in programming mode. Figure 6-5 shows a write/verify timing diagram. 121 Start Set write/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n + 1 n Yes No n < 25 Write time t PW = 1 ms 5% No Go Verify Go Write time t OPW = 3n ms No Address + 1 address Last address? Yes Set read mode VCC = 5.0 V 0.5 V, VPP = VCC Error No All addresses read? Yes End Figure 6-4 High-Performance Programming Flowchart 122 Table 6-4 DC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Input highlevel voltage Input lowlevel voltage Output highlevel voltage Output lowlevel voltage Symbol Min EO7 to EO0, EA14 to EA0, VIH OE, CE EO7 to EO0, EA14 to EA0, VIL OE, CE EO7 to EO0 EO7 to EO0 VOH VOL 2.4 -0.3 2.4 -- -- -- -- Typ -- -- -- -- -- -- -- Max Test Unit Conditions VCC + 0.3 V 0.8 -- 0.45 2 40 40 V V V A mA mA IOH = -200 A IOL = 0.8 mA VIN = 5.25 V/0.5 V Input leakage EO7 to EO0, EA14 to EA0, |ILI| current OE, CE VCC current VPP current ICC IPP Table 6-5 AC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width CE pulse width for overwrite programming VCC setup time Data output delay time Symbol tAS tOES tDS tAH tDH tDF*2 tVPS tPW tOPW*3 tVCS tOE Min 2 2 2 0 2 0 2 0.95 2.85 2 0 Typ -- -- -- -- -- -- -- 1.0 -- -- -- Max -- -- -- -- -- 130 -- 1.05 78.7 -- 500 Unit s s s s s ns s ms ms s ns Test Conditions Figure 6-5*1 Notes: 1. Input pulse level: 0.8 V to 2.2 V Input rise time/fall time 20 ns Timing reference levels Input: 1.0 V, 2.0 V Output: 0.8 V, 2.0 V 2. tDF is defined at the point at which the output is floating and the output level cannot be read. 3. tOPW is defined by the value given in figure 6-4 high-performance programming flow chart. 123 Write Address tAS Data tDS VPP VPP VCC VCC +1 VCC VCC tVCS tVPS Input data tDH Verify tAH Output data tDF CE tPW tOES tOE OE tOPW* Note: * t OPW is defined by the value given in figure 6-4 high-performance programming flow chart. Figure 6-5 PROM Write/Verify Timing 6.3.2 Programming Precautions * Use the specified programming voltage and timing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C256 will result in a correct VPP of 12.5 V. * Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure that the chip is properly mounted in the PROM programmer. Avoid touching the socket adapter or chip during programming, since this may cause contact faults and write errors. * 124 6.4 H8/3837U PROM Mode 6.4.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. Table 6-6 shows how to set the chip to PROM mode. Table 6-6 Setting to PROM Mode Pin Name TEST PB4/AN4 PB5/AN5 PB6/AN6 High level Setting High level Low level 6.4.2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM. A socket adapter is required for conversion to 32 pins, as listed in table 6-7. Figure 6-6 shows the pin-to-pin wiring of the socket adapter. Figure 6-7 shows a memory map. Table 6-7 Socket Adapter Package 100-pin (FP-100B) 100-pin (FP-100A) 100-pin (TFP-100B) Socket Adapter HS3836ESH01H HS3836ESF01H HS3836ESN01H 125 H8/3837U FP-100A 12 47 48 49 50 51 52 53 54 70 69 68 67 66 65 64 63 55 91 57 58 59 60 61 84 85 62 56 83 34, 79 92 6 8 99 13 81 82 86 9, 30 5 97 98 FP-100B 9 44 45 46 47 48 49 50 51 67 66 65 64 63 62 61 60 52 88 54 55 56 57 58 81 82 59 53 80 31, 76 89 3 5 96 10 78 79 83 6, 27 2 94 95 Pin RES P60 P61 P62 P63 P64 P65 P66 P67 P87 P86 P85 P84 P83 P82 P81 P80 P70 P43 P72 P73 P74 P75 P76 P14 P15 P77 P71 P13 VCC AVCC TEST X1 PB6 MD0 P11 P12 P16 VSS AVSS PB4 PB5 Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC EPROM socket HN27C101 (32 pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 VSS 16 Note: Pins not indicated in the figure should be left open. Figure 6-6 Socket Adapter Pin Correspondence (with HN27C101) 126 Address in MCU mode H'0000 Address in PROM mode H'0000 On-chip PROM H'EDFF H'EDFF Missing area * H'1FFFF Note: * If read in PROM mode, this address area returns unpredictable output data. When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If address H'EE00 and higher addresses are programmed by mistake, it may become impossible to program the PROM or verify the programmed data. When programming, assign H'FF data to this address area (H'EE00 to H'1FFFF). Figure 6-7 H8/3837U Memory Map in PROM Mode 127 6.5 H8/3837U Programming The write, verify, and other modes are selected as shown in table 6-8 in H8/3837U PROM mode. Table 6-8 Mode Selection in H8/3837U PROM Mode Pin Mode Write Verify Programming disabled CE L L L L H H Notation L: Low level H: High level VPP: VPP level VCC: VCC level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA16 to EA0 Address input Address input Address input The specifications for writing and reading the on-chip PROM are identical to those for the standard HN27C101 EPROM. Page programming is not supported, however. The PROM writer must not be set to page mode. A PROM programmer that provides only page programming mode cannot be used. When selecting a PROM programer, check that it supports a byte-by-byte highspeed, high-reliability programming method. Be sure to set the address range to H'0000 to H'EDFF. 6.5.1 Writing and Verifying An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. The basic flow of this high-speed, high-reliability programming method is shown in figure 6-8. 128 Start Set write/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n+1 n No Yes n < 25 Write time t PW = 0.2 ms 5% No Go Verify Go Write time t OPW = 0.2n ms No Address + 1 address Last address? Yes Set read mode VCC = 5.0 V 0.25 V, VPP = VCC No Error All addresses read? Yes End Figure 6-8 High-Speed, High-Reliability Programming Flow Chart 129 Table 6-9 and table 6-10 give the electrical characteristics in programming mode. Table 6-9 DC Characteristics (preliminary) (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Input highlevel voltage Input lowlevel voltage Output highlevel voltage Output lowlevel voltage EO7 to EO0, EA16 to EA0 OE, CE, PGM EO7 to EO0, EA16 to EA0 OE, CE, PGM EO7 to EO0 EO7 to EO0 Symbol VIH VIL VOH VOL |ILI| ICC IPP Min 2.4 -0.3 2.4 -- -- -- -- Typ -- -- -- -- -- -- -- Max Test Unit Conditions VCC + 0.3 V 0.8 -- 0.45 2 40 40 V V V A mA mA IOH = -200 A IOL = 0.8 mA Vin = 5.25 V/ 0.5 V Input leakage EO7 to EO0, EA16 to EA0 current OE, CE, PGM VCC current VPP current 130 Table 6-10 AC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width PGM pulse width for overwrite programming VCC setup time CE setup time Data output delay time Symbol tAS tOES tDS tAH tDH tDF*2 tVPS tPW tOPW*3 tVCS tCES tOE Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 200 Unit s s s s s ns s ms ms s s ns Test Conditions Figure 6-9*1 Notes: 1. Input pulse level: 0.45 V to 2.4 V Input rise time/fall time 20 ns Timing reference levels Input: 0.8 V, 2.0 V Output: 0.8 V, 2.0 V 2. tDF is defined at the point at which the output is floating and the output level cannot be read. 3. tOPW is defined by the value given in figure 6-8 high-speed, high-reliability programming flow chart. 131 Figure 6-9 shows a write/verify timing diagram. Write Address tAS Data tDS VPP VPP VCC VCC +1 VCC tVCS tVPS Input data tDH Verify tAH Output data tDF VCC CE tCES PGM tPW OE tOPW* tOES tOE Note: * tOPW is defined by the value given in figure 6-8 high-speed, high-reliability programming flow chart. Figure 6-9 PROM Write/Verify Timing 132 6.5.2 Programming Precautions * Use the specified programming voltage and timing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in correct VPP of 12.5 V. * Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure that the chip is properly mounted in the PROM programmer. Avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. Select the programming mode carefully. The chip cannot be programmed in page programming mode. When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If address H'EE00 and higher addresses are programmed by mistake, it may become impossible to program the PROM or verify the programmed data. When programming, assign H'FF data to the address area from H'EE00 to H'1FFFF. * * * 133 6.6 Reliability of Programmed Data A highly effective way of assuring data retention characteristics after programming is to screen the chips by baking them at a temperature of 150C. This quickly eliminates PROM memory cells prone to initial data retention failure. Figure 6-10 shows a flowchart of this screening procedure. Write program and verify contents Bake at high temperature with power off 125C to 150C, 24 hrs to 48 hrs Read and check program Install Figure 6-10 Recommended Screening Procedure If write errors occur repeatedly while the same PROM programmer is being used, stop programming and check for problems in the PROM programmer and socket adapter, etc. Please notify your Hitachi representative of any problems occurring during programming or in screening after high-temperature baking. 134 Section 7 RAM 7.1 Overview The H8/3833U and H8/3834U have 1 kbyte of high-speed static RAM on-chip, while the H8/3835U, H8/3836U, and H8/3837U each have 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 Block Diagram Figure 7-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FB80 H'FB82 H'FB80 H'FB82 H'FB81 H'FB83 On-chip RAM H'FF7E H'FF7E Even-numbered address H'FF7F Odd-numbered address Figure 7-1 RAM Block Diagram (H8/3834U) 135 Section 8 I/O Ports 8.1 Overview The H8/3834U Series is provided with eight 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port, one 8-bit input-only port, one 4-bit input-only port, and one 1-bit input-only port. Table 8-1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits. See 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions to write data in PCR or PDR. Ports 5, 6, 7, 8, 9, and A double as LCD segment pins and common pins. The choice of pin functions can be made in 4-bit groupings. Block diagrams of each port are given in Appendix C. Table 8-1 Port Functions Function Switching Register PMR1 TCRF, TMC, TMB PMR1 PMR1 PMR1 PMR1 Port Port 1 Description * 8-bit I/O port * Input pull-up MOS option Pins P17 to P15/ IRQ3 to IRQ1/ TMIF, TMIC, TMIB P14/PWM P13/TMIG Other Functions External interrupts 3 to 1 Timer event input TMIF, TMIC, TMIB 14-bit PWM output Timer G input capture Timer F output compare P12, P11/ TMOFH, TMOFL P10/TMOW Port 2 * 8-bit I/O port * Open drain output option * High-current port P27 to P22 P21/UD P20/IRQ4/ ADTRG Timer A clock output None Timer C count-up/down selection External interrupt 4 and A/D converter external trigger PMR2 PMR2 AMR 137 Table 8-1 Port Functions (cont) Function Switching Register PMR3 Port Port 3 Description * 8-bit I/O port * Input pull-up MOS option * High-current port Pins P37/CS P36/STRB P35/SO2 P34/SI2 P33/SCK2 P32/SO1 P31/SI1 P30/SCK1 Other Functions SCI2 chip select input (CS), strobe output (STRB), data output (SO2), data input (SI2), clock input/output (SCK2) SCI1 data output (SO1), data input (SI1), clock input/output (SCK1) External interrupt 0 SCI3 data output (TXD), data input (RXD), clock input/output (SCK3) * Wakeup input (WKP7 to WKP0) * Segment output (SEG8 to SEG1) Segment output (SEG16 to SEG9) PMR3 Port 4 * 1-bit input-only port P43/IRQ0 * 3-bit I/O port P42/TXD P41/RXD P40/SCK3 * 8-bit I/O port * Input pull-up MOS option * 8-bit I/O port * Input pull-up MOS option * 8-bit I/O port * 8-bit I/O port * 8-bit I/O port P57 to P50/ WKP7 to WKP0/ SEG8 to SEG1 P67 to P60/ SEG16 to SEG9 PMR2 SCR3 SMR3 PMR5 LPCR LPCR Port 5 Port 6 Port 7 Port 8 Port 9 Segment output (SEG24 to SEG17) P77 to P70/ SEG24 to SEG17 P87 to P80/ Segment output (SEG32 to SEG25) SEG32 to SEG25 LPCR LPCR P97/SEG40/CL1 * Segment output (SEG40 to SEG37) LPCR P96/SEG39/CL2 * Latch clock (CL1), for external P95/SEG38/DO segment expansion, shift clock P94/SEG37/M (CL2), display data port (DO), P93 to P90/ and alternating signal (M) SEG36 to SEG33 * Segment output (SEG36 to SEG33) PA3 to PA0/ COM4 to COM1 PB7 to PB0/ AN7 to AN0 PC3 to PC0/ AN11 to AN8 Common output (COM4 to COM1) A/D converter analog input A/D converter analog input LPCR AMR AMR Port A Port B Port C * 4-bit I/O port * 8-bit input port * 4-bit input port 138 8.2 Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Figure 8-1 shows its pin configuration. P1 7 /IRQ 3 /TMIF P1 6 /IRQ 2 /TMIC P1 5 /IRQ 1 /TMIB Port 1 P1 4 /PWM P1 3 /TMIG P1 2 /TMOFH P1 1 /TMOFL P1 0 /TMOW Figure 8-1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8-2 shows the port 1 register configuration. Table 8-2 Port 1 Registers Name Port data register 1 Port control register 1 Port pull-up control register 1 Port mode register 1 Abbrev. PDR1 PCR1 PUCR1 PMR1 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD4 H'FFE4 H'FFE0 H'FFC8 139 1. Bit Port data register 1 (PDR1) 7 P1 7 0 R/W 6 P1 6 0 R/W 5 P1 5 0 R/W 4 P1 4 0 R/W 3 P1 3 0 R/W 2 P1 2 0 R/W 1 P1 1 0 R/W 0 P1 0 0 R/W Initial value Read/Write PDR1 is an 8-bit register that stores data for pins P17 through P10. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Upon reset, PDR1 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 1 (PCR1) 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 to P10 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. Upon reset, PCR1 is initialized to H'00. PCR1 is a write-only register. All bits are read as 1. 3. Bit Initial value Read/Write Port pull-up control register 1 (PUCR1) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 PUCR1 controls whether the MOS pull-up of each port 1 pin is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR1 is initialized to H'00. 140 4. Bit Port mode register 1 (PMR1) 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 PWM 0 R/W 3 TMIG 0 R/W 2 TMOFH 0 R/W 1 TMOFL 0 R/W 0 TMOW 0 R/W Initial value Read/Write PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7: P17/IRQ3/TMIF pin function switch (IRQ3) This bit selects whether pin P17/IRQ3/TMIF is used as P17 or as IRQ3/TMIF. Bit 7 IRQ3 0 1 Description Functions as P17 I/O pin Functions as IRQ3/TMIF input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ3/TMIF. For details on TMIF pin settings, see 9.5.2 (3), timer control register F (TCRF). Bit 6: P16/IRQ2/TMIC pin function switch (IRQ2) This bit selects whether pin P16/IRQ2/TMIC is used as P16 or as IRQ2/TMIC. Bit 6 IRQ2 0 1 Description Functions as P16 I/O pin Functions as IRQ2/TMIC input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ2/TMIC. For details on TMIC pin settings, see 9.4.2 (1), timer mode register C (TMC). Bit 5: P15/IRQ1/TMIB pin function switch (IRQ1) This bit selects whether pin P15/IRQ1/TMIB is used as P15 or as IRQ1/TMIB. Bit 5 IRQ1 0 1 Description Functions as P15 I/O pin Functions as IRQ1/TMIB input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ1/TMIB. For details on TMIB pin settings, see 9.3.2 (1), timer mode register B (TMB). 141 Bit 4: P14/PWM pin function switch (PWM) This bit selects whether pin P14/PWM is used as P14 or as PWM. Bit 4 PWM 0 1 Description Functions as P14 I/O pin Functions as PWM output pin (initial value) Bit 3: P13/TMIG pin function switch (TMIG) This bit selects whether pin P13/TMIG is used as P13 or as TMIG. Bit 3 TMIG 0 1 Description Functions as P13 I/O pin Functions as TMIG input pin (initial value) Bit 2: P12/TMOFH pin function switch (TMOFH) This bit selects whether pin P12/TMOFH is used as P12 or as TMOFH. Bit 2 TMOFH 0 1 Description Functions as P12 I/O pin Functions as TMOFH output pin (initial value) Bit 1: P11/TMOFL pin function switch (TMOFL) This bit selects whether pin P11/TMOFL is used as P11 or as TMOFL. Bit 1 TMOFL 0 1 Description Functions as P11 I/O pin Functions as TMOFL output pin (initial value) 142 Bit 0: P10/TMOW pin function switch (TMOW) This bit selects whether pin P10/TMOW is used as P10 or as TMOW. Bit 0 TMOW 0 1 Descrition Functions as P10 I/O pin Functions as TMOW output pin (initial value) 8.2.3 Pin Functions Table 8-3 shows the port 1 pin functions. Table 8-3 Port 1 Pin Functions Pin P17/IRQ3/TMIF Pin Functions and Selection Method The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR17 in PCR1. IRQ3 PCR17 CKSL2 to CKSL0 Pin function 0 * 0 1 Not 0** 1 * 0** IRQ3/TMIF input pin P17 input pin P17 output pin IRQ3 input pin Note: When using as TMIF input pin, clear bit IEN3 in IENR1 to 0, disabling IRQ3 interrupts. P16/IRQ2/TMIC The pin function depends on bit IRQ2 in PMR1, bits TMC2 to TMC0 in TMC, and bit PCR16 in PCR1. IRQ2 PCR16 TMC2 to TMC0 Pin function 0 * 0 1 Not 111 1 * 111 IRQ2/TMIC input pin P16 input pin P16 output pin IRQ2 input pin Note: When using as TMIC input pin, clear bit IEN2 in IENR1 to 0, disabling IRQ2 interrupts. Note: * Don't care 143 Table 8-3 Port 1 Pin Functions (cont) Pin Pin Functions and Selection Method P15/IRQ1/ TMIB The pin function depends on bit IRQ1 in PMR1, bits TMB2 to TMB0 in TMB, and bit PCR15 in PCR1. IRQ1 PCR15 TMB2 to TMB0 Pin function 0 * 0 1 Not 111 1 * 111 IRQ1/TMIB input pin P15 input pin P15 output pin IRQ1 input pin Note: When using as TMIB input pin, clear bit IEN1 in IENR1 to 0, disabling IRQ1 interrupts. P14/PWM The pin function depends on bit PWM in PMR1 and bit PCR14 in PCR1. PWM PCR14 Pin function P13/TMIG 0 0 1 1 * PWM output pin P14 input pin P14 output pin The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1. TMIG PCR13 Pin function 0 0 1 1 * TMIG input pin P13 input pin P13 output pin P12/TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1. TMOFH PCR12 Pin function 0 0 1 1 * TMOFH output pin P12 input pin P12 output pin P11/TMOFL The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1. TMOFL PCR11 Pin function 0 0 1 1 * TMOFL output pin P11 input pin P11 output pin P10/TMOW The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1. TMOW PCR10 Pin function 0 0 1 1 * TMOW output pin P10 input pin P10 output pin Note: * Don't care 144 8.2.4 Pin States Table 8-4 shows the port 1 pin states in each operating mode. Table 8-4 Port 1 Pin States Pins P17/IRQ3/TMIF P16/IRQ2/TMIC P15/IRQ1/TMIB P14/PWM P13/TMIG P12/TMOFH P11/TMOFL P10/TMOW Reset Sleep Subsleep Retains previous state Standby Highimpedance* Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.2.5 MOS Input Pull-Up Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset. PCR1n PUCR1n MOS input pull-up Note: * Don't care n = 7 to 0 0 Off 0 1 On 1 * Off 145 8.3 Port 2 8.3.1 Overview Port 2 is an 8-bit I/O port. Figure 8-2 shows its pin configuration. P2 7 P2 6 P2 5 Port 2 P2 4 P2 3 P2 2 P2 1 /UD P2 0 /IRQ 4/ADTRG Figure 8-2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8-5 shows the port 2 register configuration. Table 8-5 Port 2 Registers Name Port data register 2 Port control register 2 Port mode register 2 Port mode register 4 Abbrev. PDR2 PCR2 PMR2 PMR4 R/W R/W W R/W R/W Initial Value H'00 H'00 H'C0 H'00 Address H'FFD5 H'FFE5 H'FFC9 H'FFCB 146 1. Bit Port data register 2 (PDR2) 7 P2 7 0 R/W 6 P2 6 0 R/W 5 P25 0 R/W 4 P2 4 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P2 0 0 R/W Initial value Read/Write PDR2 is an 8-bit register that stores data for pins P27 through P20. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read. Upon reset, PDR2 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 2 (PCR2) 7 PCR27 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 PCR23 0 W 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W PCR2 is an 8-bit register for controlling whether each of the port 2 pins P27 to P20 functions as an input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and in PDR2 are valid only when the corresponding pin is designated in PMR2 as a general I/O pin. Upon reset, PCR2 is initialized to H'00. PCR2 is a write-only register. All bits are read as 1. 3. Bit Initial value Read/Write Port mode register 2 (PMR2) 7 -- 1 -- 6 -- 1 -- 5 POF2 0 R/W 4 NCS 0 R/W 3 IRQ0 0 R/W 2 POF1 0 R/W 1 UD 0 R/W 0 IRQ4 0 R/W PMR2 is an 8-bit read/write register, controlling the selection of pin functions for pins P20, P21,and P43, controlling the PMOS on/off option for pins P35/SO2 and P32/SO1, and controlling the TMIG input noise canceller. Upon reset, PMR2 is initialized to H'C0. 147 Bits 7 to 6: Reserved bits Bits 7 to 6 are reserved; they are always read as 1, and cannot be modified. Bit 5: P35/SO2 pin PMOS control (POF2) This bit controls the PMOS transistor in the P35/SO2 pin output buffer. Bit 5 POF2 0 1 Description CMOS output NMOS open-drain output (initial value) Bit 4: TMIG noise canceller select (NCS) This bit controls the noise canceller circuit for input capture at pin TMIG. Bit 4 NCS 0 1 Description Noise canceller function not selected Noise canceller function selected (initial value) Bit 3: P43/IRQ0 pin function switch (IRQ0) This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0. Bit 3 IRQ0 0 1 Description Functions as P43 input pin Functions as IRQ0 input pin (initial value) Bit 2: P32/SO1 pin PMOS control (POF1) This bit controls the PMOS transistor in the P32/SO1 pin output buffer. Bit 2 POF1 0 1 Description CMOS output NMOS open-drain output (initial value) 148 Bit 1: P21/UD pin function switch (UD) This bit selects whether pin P21/UD is used as P21 or as UD. Bit 1 UD 0 1 Description Functions as P21 I/O pin Functions as UD input pin (initial value) Bit 0: P20/IRQ4/ADTRG pin function switch (IRQ4) This bit selects whether pin P20/IRQ4/ADTRG is used as P20 or as IRQ4/ADTRG. Bit 0 IRQ4 0 1 Description Functions as P20 I/O pin Functions as IRQ4/ADTRG input pin (initial value) Note: See 12.3.2, Start of A/D Conversion by External Trigger Input, for the ADTRG pin setting. 4. Bit Port mode register 4 (PMR4) 7 NMOD 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W NMOD 6 NMOD 5 NMOD4 NMOD3 NMOD 2 NMOD1 NMOD 0 Initial value Read/Write PMR4 is an 8-bit read/write register, used to select CMOS output or NMOS open drain output for each port 2 pin. Upon reset, PMR4 is initialized to H'00. Bit n: NMOS open-drain output select (NMODn) This bit selects CMOS output or NMOS open-drain output when pin P2n is used as an output pin. Bit n NMODn 0 1 Description CMOS output NMOS open-drain output (n = 7 to 0) 149 8.3.3 Pin Functions Table 8-6 shows the port 2 pin functions. Table 8-6 Port 2 Pin Functions Pin P27 to P22 Pin Functions and Selection Method Input or output is selected as follows by the bit settings in PCR2. (n = 2 to 7) PCR2n Pin function P21/UD 0 P2n input pin 1 P2n output pin The pin function depends on bit UD in PMR2 and bit PCR21 in PCR2. UD PCR21 Pin function 0 0 1 1 * UD input pin P21 input pin P21 output pin P20/IRQ4/ADTRG The pin function depends on bit IRQ4 in PMR2, bit TRGE in AMR, and bit PCR20 in PCR2. IRQ4 PCR20 TRGE Pin function 0 * P20 input pin P20 output pin 0 1 0 IRQ4 input pin 1 * 1 IRQ4/ADTRG input pin Note: When using as ADTRG input pin, clear bit IEN4 in IENR1 to 0, disabling IRQ4 interrupts. Note: * Don't care 8.3.4 Pin States Table 8-7 shows the port 2 pin states in each operating mode. Table 8-7 Port 2 Pin States Pins P27 to P22 P21/UD P20/IRQ4/ ADTRG Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state 150 8.4 Port 3 8.4.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8-3. P3 7 /CS P3 6 /STRB P3 5 /SO 2 Port 3 P3 4 /SI 2 P3 3 /SCK 2 P3 2 /SO 1 P3 1 /SI1 P3 0 /SCK1 Figure 8-3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description Table 8-8 shows the port 3 register configuration. Table 8-8 Port 3 Registers Name Port data register 3 Port control register 3 Port pull-up control register 3 Port mode register 3 Abbrev. PDR3 PCR3 PUCR3 PMR3 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD6 H'FFE6 H'FFE1 H'FFCA 151 1. Bit Port data register 3 (PDR3) 7 P3 7 0 R/W 6 P3 6 0 R/W 5 P35 0 R/W 4 P3 4 0 R/W 3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P3 0 0 R/W Initial value Read/Write PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read. Upon reset, PDR3 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 3 (PCR3) 7 PCR37 0 W 6 PCR36 0 W 5 PCR35 0 W 4 PCR34 0 W 3 PCR33 0 W 2 PCR32 0 W 1 PCR31 0 W 0 PCR30 0 W PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P30 functions as an input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I/O pin. Upon reset, PCR3 is initialized to H'00. PCR3 is a write-only register. All bits are read as 1. 3. Bit Initial value Read/Write Port pull-up control register 3 (PUCR3) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 PUCR3 controls whether the MOS pull-up of each port 3 pin is on or off. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR3 is initialized to H'00. 152 4. Bit Port mode register 3 (PMR3) 7 CS 0 R/W 6 STRB 0 R/W 5 SO2 0 R/W 4 SI2 0 R/W 3 SCK2 0 R/W 2 SO1 0 R/W 1 SI1 0 R/W 0 SCK1 0 R/W Initial value Read/Write PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'00. Bit 7: P37/CS pin function switch (CS) This bit selects whether pin P37/CS is used as P37 or as CS. Bit 7 CS 0 1 Description Functions as P37 I/O pin Functions as CS input pin (initial value) Bit 6: P36/STRB pin function switch (STRB) This bit selects whether pin P36/STRB is used as P36 or as STRB. Bit 6 STRB 0 1 Description Functions as P36 I/O pin Functions as STRB output pin (initial value) Bit 5: P35/SO2 pin function switch (SO2) This bit selects whether pin P35/SO2 is used as P35 or as SO2. Bit 5 SO2 0 1 Description Functions as P35 I/O pin Functions as SO2 output pin (initial value) 153 Bit 4: P34/SI2 pin function switch (SI2) This bit selects whether pin P34/SI2 is used as P34 or as SI2. Bit 4 SI2 0 1 Description Functions as P34 I/O pin Functions as SI2 input pin (initial value) Bit 3: P33/SCK2 pin function switch (SCK2) This bit selects whether pin P33/SCK2 is used as P33 or as SCK2. Bit 3 SCK2 0 1 Description Functions as P33 I/O pin Functions as SCK2 I/O pin (initial value) Bit 2: P32/SO1 pin function switch (SO1) This bit selects whether pin P32/SO1 is used as P32 or as SO1. Bit 2 SO1 0 1 Description Functions as P32 I/O pin Functions as SO1 output pin (initial value) Bit 1: P31/SI1 pin function switch (SI1) This bit selects whether pin P31/SI1 is used as P31 or as SI1. Bit 1 SI1 0 1 Description Functions as P31 I/O pin Functions as SI1 input pin (initial value) 154 Bit 0: P30/SCK1 pin function switch (SCK1) This bit selects whether pin P30/SCK1 is used as P30 or as SCK1. Bit 0 SCK1 0 1 Description Functions as P30 I/O pin Functions as SCK1 I/O pin (initial value) 8.4.3 Pin Functions Table 8-9 shows the port 3 pin functions. Table 8-9 Port 3 Pin Functions Pin P37/CS Pin Functions and Selection Method The pin function depends on bit CS in PMR3 and bit PCR37 in PCR3. CS PCR37 Pin function P36/STRB 0 0 1 1 * CS input pin P37 input pin P37 output pin The pin function depends on bit STRB in PMR3 and bit PCR36 in PCR3. STRB PCR36 Pin function 0 0 1 1 * STRB output pin P36 input pin P36 output pin P35/SO2 The pin function depends on bit SO2 in PMR3 and bit PCR35 in PCR3. SO2 PCR35 Pin function 0 0 1 1 * SO2 output pin P35 input pin P35 output pin P34/SI2 The pin function depends on bit SI2 in PMR3 and bit PCR34 in PCR3. SI2 PCR34 Pin function 0 0 1 1 * SI2 input pin P34 input pin P34 output pin Note: * Don't care 155 Table 8-9 Port 3 Pin Functions (cont) Pin P33/SCK2 Pin Functions and Selection Method The pin function depends on bit SCK2 in PMR3, bits CKS2 to 0 in SCR2, and bit PCR33 in PCR3. SCK2 CKS2 to CKS0 PCR33 Pin function P32/SO1 0 0 * 1 Not 111 * 1 111 * P33 input pin P33 output pin SCK2 output pin SCK2 input pin The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3. SO1 PCR32 Pin function 0 0 1 1 * SO1 output pin P32 input pin P32 output pin P31/SI1 The pin function depends on bit SI1 in PMR3 and bit PCR31 in PCR3. SI1 PCR31 Pin function 0 0 1 1 * SI1 input pin P31 input pin P31 output pin P30/SCK1 The pin function depends on bit SCK1 in PMR3, bit CKS3 in SCR1, and bit PCR30 in PCR3. SCK1 CKS3 PCR30 Pin function 0 0 * 1 0 * 1 1 * P30 input pin P30 output pin SCK1 output pin SCK1 input pin Note: * Don't care 156 8.4.4 Pin States Table 8-10 shows the port 3 pin states in each operating mode. Table 8-10 Port 3 Pin States Pins P37/CS P36/STRB P35/SO2 P34/SI2 P33/SCK2 P32/SO1 P31/SI1 P30/SCK1 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Watch Subactive Active HighRetains Functional Functional impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.4.5 MOS Input Pull-Up Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR3n PUCR3n MOS input pull-up Note: * Don't care 0 Off 0 1 On 1 * Off (n = 7 to 0) 157 8.5 Port 4 8.5.1 Overview Port 4 consists of a 3-bit I/O port and a 1-bit input port, and is configured as shown in figure 8-4. P4 3 /IRQ 0 Port 4 P4 2 /TXD P4 1 /RXD P4 0 /SCK 3 Figure 8-4 Port 4 Pin Configuration 8.5.2 Register Configuration and Description Table 8-11 shows the port 4 register configuration. Table 8-11 Port 4 Registers Name Port data register 4 Port control register 4 Abbrev. PDR4 PCR4 R/W R/W W Initial Value H'F8 H'F8 Address H'FFD7 H'FFE7 158 1. Bit Port data register 4 (PDR4) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 P43 1 R 2 P42 0 R/W 1 P41 0 R/W 0 P4 0 0 R/W Initial value Read/Write PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is read while PCR4 bits are cleared to 0, the pin states are read. Upon reset, PDR4 is initialized to H'F8. 2. Bit Initial value Read/Write Port control register 4 (PCR4) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 PCR42 0 W 1 PCR41 0 W 0 PCR4 0 0 W PCR4 controls whether each of the port 4 pins P42 to P40 functions as an input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR4 and in PDR4 are valid only when the corresponding pin is designated in SCR3 as a general I/O pin. Upon reset, PCR4 is initialized to H'F8. PCR4 is a write-only register. All bits are read as 1. 159 8.5.3 Pin Functions Table 8-12 shows the port 4 pin functions. Table 8-12 Port 4 Pin Functions Pin P43/IRQ0 Pin Functions and Selection Method The pin function depends on the IRQ0 bit setting in PMR2. IRQ0 Pin function P42/TXD 0 P43 input pin 1 IRQ0 input pin The pin function depends on bit TE in SCR3 and bit PCR42 in PCR4. UD PCR42 Pin function 0 0 1 1 * TXD output pin P42 input pin P42 output pin P41/RXD The pin function depends on bit RE in SCR3 and bit PCR41 in PCR4. RE PCR41 Pin function 0 0 1 1 * RXD input pin P41 input pin P41 output pin P40/SCK3 The pin function depends on bits CKE1 and CKE0 in SCR3, bit COM in SMR, and bit PCR40 in PCR4. CKE1 CKE0 COM PCR40 Pin function 0 0 1 0 1 * 0 1 * 1 * * * P40 input pin P40 output pin SCK3 output pin SCK3 input pin Note: * Don't care 160 8.5.4 Pin States Table 8-13 shows the port 4 pin states in each operating mode. Table 8-13 Port 4 Pin States Pins P43/IRQ0 P42/TXD P41/RXD P40/SCK3 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state 161 8.6 Port 5 8.6.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8-5. P5 7 /WKP7 /SEG 8 P5 6 /WKP6 /SEG 7 P5 5 /WKP5 /SEG 6 Port 5 P5 4 /WKP4 /SEG 5 P5 3 /WKP3 /SEG 4 P5 2 /WKP2 /SEG 3 P5 1 /WKP1 /SEG 2 P5 0 /WKP0 /SEG 1 Figure 8-5 Port 5 Pin Configuration 8.6.2 Register Configuration and Description Table 8-14 shows the port 5 register configuration. Table 8-14 Port 5 Registers Name Port data register 5 Port control register 5 Port pull-up control register 5 Port mode register 5 Abbrev. PDR5 PCR5 PUCR5 PMR5 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD8 H'FFE8 H'FFE2 H'FFCC 162 1. Bit Port data register 5 (PDR5) 7 P5 7 0 R/W 6 P5 6 0 R/W 5 P55 0 R/W 4 P5 4 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P5 0 0 R/W Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. Upon reset, PDR5 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 5 (PCR5) 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W 2 PCR52 0 W 1 PCR51 0 W 0 PCR50 0 W PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR5 and in PDR5 are valid only when the corresponding pin is designated as a general I/O pin in PMR5 and in bits SGS3 to SGS0 of LPCR. Upon reset, PCR5 is initialized to H'00. PCR5 is a write-only register. All bits are read as 1. 3. Bit Initial value Read/Write Port pull-up control register 5 (PUCR5) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR5 controls whether the MOS pull-up of each port 5 pin is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR5 is initialized to H'00. 163 4. Bit Port mode register 5 (PMR5) 7 WKP7 0 R/W 6 WKP6 0 R/W 5 WKP5 0 R/W 4 WKP4 0 R/W 3 WKP3 0 R/W 2 WKP2 0 R/W 1 WKP1 0 R/W 0 WKP0 0 R/W Initial value Read/Write PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n: P5n/WKPn/SEGn+1 pin function switch (WKPn) When pin P5n/WKPn/SEGn+1 is not used as a SEGn+1 pin, this bit selects whether it is used as P5n or as WKPn. Bit n WKPn 0 1 Description Functions as P5n I/O pin Functions as WKPn input pin (n = 7 to 0) (initial value) Note: For information on use as a SEGn+1 pin, see 13.2.1, LCD Port Control Register (LPCR). 164 8.6.3 Pin Functions Table 8-15 shows the port 5 pin functions. Table 8-15 Port 5 Pin Functions Pin P57/WKP7/ SEG8to P54/ WKP4/SEG5 Pin Functions and Selection Method The pin function depends on bit WKPn in PMR5, bit PCR5n in PCR5, and bits SGS3 to SGS0 in LPCR. (n = 7 to 4) SGS3 to SGS0 WKPn PCR5n Pin function P53/WKP3/ SEG4 to P50/ WKP0/SEG1 0 0 1 0*** 1 * 1*** * * P5n input pin P5n output pin WKPn input pin SEGn+1 output pin The pin function depends on bit WKPn in PMR5, bit PCR5n in PCR5, and bits SGS3 to SGS0 in LPCR. (n = 3 to 0) SGS3 to SGS0 WKPn PCR5n Pin function 0 0 1 0*** or 1**0 1 * 1**1 * * P5n input pin P5n output pin WKPn input pin SEGn+1 output pin Note: * Don't care 165 8.6.4 Pin States Table 8-16 shows the port 5 pin states in each operating mode. Table 8-16 Port 5 Pin States Pins Reset Sleep Subsleep Retains previous state Standby Watch Subactive Active Functional HighRetains P57/WKP7/ SEG8 to P50/ impedance previous WKP0/SEG1 state HighRetains Functional impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.6.5 MOS Input Pull-Up Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR5n PUCR5n MOS input pull-up Note: * Don't care 0 Off 0 1 On 1 * Off (n = 7 to 0) 166 8.7 Port 6 8.7.1 Overview Port 6 is an 8-bit I/O port, configured as shown in figure 8-6. P6 7 /SEG 16 P6 6 /SEG 15 P6 5 /SEG 14 Port 6 P6 4 /SEG 13 P6 3 /SEG 12 P6 2 /SEG 11 P6 1 /SEG 10 P6 0 /SEG 9 Figure 8-6 Port 6 Pin Configuration 8.7.2 Register Configuration and Description Table 8-17 shows the port 6 register configuration. Table 8-17 Port 6 Registers Name Port data register 6 Port control register 6 Port pull-up control register 6 Abbrev. PDR6 PCR6 PUCR6 R/W R/W W R/W Initial Value H'00 H'00 H'00 Address H'FFD9 H'FFE9 H'FFE3 167 1. Bit Port data register 6 (PDR6) 7 P6 7 0 R/W 6 P6 6 0 R/W 5 P65 0 R/W 4 P6 4 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P6 0 0 R/W Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60. If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read. Upon reset, PDR6 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 6 (PCR6) 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 2 PCR62 0 W 1 PCR61 0 W 0 PCR60 0 W PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an input pin or output pin. Setting a PCR6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR6 and in PDR6 are valid only when the corresponding pin is designated in bits SGS3 to SGS0 in LPCR as a general I/O pin. Upon reset, PCR6 is initialized to H'00. PCR6 is a write-only register. All bits are read as 1. 3. Bit Initial value Read/Write Port pull-up control register 6 (PUCR6) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 PUCR6 controls whether the MOS pull-up of each port 6 pin is on or off. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR6 is initialized to H'00. 168 8.7.3 Pin Functions Table 8-18 shows the port 6 pin functions. Table 8-18 Port 6 Pin Functions Pin P67/SEG16 to P64/SEG13 Pin Functions and Selection Method The pin function depends on bit PCR6n in PCR6 and bits SGS3 to SGS0 in LPCR. (n = 7 to 4) SGS3 to SGS0 PCR6n Pin function P63/SEG12 to P60/SEG9 0 00** or 010* 1 011* or 1*** * SEGn+9 output pin P6n input pin P6n output pin The pin function depends on bit PCR6n in PCR6 and bits SGS3 to SGS0 in LPCR. (n = 3 to 0) SGS3 to SGS0 PCR6n Pin function 00**, 010* or 0110 0 1 0111 or 1*** * SEGn+9 output pin P6n input pin P6n output pin Note: * Don't care 8.7.4 Pin States Table 8-19 shows the port 6 pin states in each operating mode. Table 8-19 Port 6 Pin States Pins P67/SEG16 to P60/SEG9 Reset Sleep Subsleep Retains previous state Standby Highimpedance* Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 169 8.7.5 MOS Input Pull-Up Port 6 has a built-in MOS input pull-up function that can be controlled by software. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR6n PUC6n MOS input pull-up Note: * Don't care 0 Off 0 1 On 1 * Off (n = 7 to 0) 170 8.8 Port 7 8.8.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8-7. P7 7 /SEG 24 P7 6 /SEG 23 P7 5 /SEG 22 Port 7 P7 4 /SEG 21 P7 3 /SEG 20 P7 2 /SEG 19 P7 1 /SEG 18 P7 0 /SEG 17 Figure 8-7 Port 7 Pin Configuration 8.8.2 Register Configuration and Description Table 8-20 shows the port 7 register configuration. Table 8-20 Port 7 Registers Name Port data register 7 Port control register 7 Abbrev. PDR7 PCR7 R/W R/W W Initial Value H'00 H'00 Address H'FFDA H'FFEA 171 1. Bit Port data register 7 (PDR7) 7 P7 7 0 R/W 6 P7 6 0 R/W 5 P75 0 R/W 4 P7 4 0 R/W 3 P73 0 R/W 2 P72 0 R/W 1 P71 0 R/W 0 P7 0 0 R/W Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read. Upon reset, PDR7 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 7 (PCR7) 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W 2 PCR72 0 W 1 PCR71 0 W 0 PCR70 0 W PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR7 and in PDR7 are valid only when the corresponding pin is designated in bits SGS3 to SGS0 in LPCR as a general I/O pin. Upon reset, PCR7 is initialized to H'00. PCR7 is a write-only register. All bits are read as 1. 172 8.8.3 Pin Functions Table 8-21 shows the port 7 pin functions. Table 8-21 Port 7 Pin Functions Pin P77/SEG24 to P74/SEG21 Pin Functions and Selection Method The pin function depends on bit PCR7n in PCR7 and bits SGS3 to SGS0 in LPCR. (n = 7 to 4) SGS3 to SGS0 PCR7n Pin function P73/SEG20 to P70/SEG17 0 00** 1 01** or 1*** * SEGn+17 output pin P7n input pin P7n output pin The pin function depends on bit PCR7n in PCR7 and bits SGS3 to SGS0 in LPCR. (n = 3 to 0) SGS3 to SGS0 PCR7n Pin function 0 00** or 0100 1 0101, 011* or 1*** * SEGn+17 output pin P7n input pin P7n output pin Note: * Don't care 8.8.4 Pin States Table 8-22 shows the port 7 pin states in each operating mode. Table 8-22 Port 7 Pin States Pins P77/SEG24 to P70/SEG17 Reset Sleep Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state 173 8.9 Port 8 8.9.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8-9. P8 7 /SEG 32 P8 6 /SEG 31 P8 5 /SEG 30 Port 8 P8 4 /SEG 29 P8 3 /SEG 28 P8 2 /SEG 27 P8 1 /SEG 26 P8 0 /SEG 25 Figure 8-8 Port 8 Pin Configuration 8.9.2 Register Configuration and Description Table 8-23 shows the port 8 register configuration. Table 8-23 Port 8 Registers Name Port data register 8 Port control register 8 Abbrev. PDR8 PCR8 R/W R/W W Initial Value H'00 H'00 Address H'FFDB H'FFEB 174 1. Bit Port data register 8 (PDR8) 7 P8 7 0 R/W 6 P8 6 0 R/W 5 P85 0 R/W 4 P8 4 0 R/W 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P8 0 0 R/W Initial value Read/Write PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. Upon reset, PDR8 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 8 (PCR8) 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W 1 PCR81 0 W 0 PCR80 0 W PCR8 is an 8-bit register for controlling whether each of the port 8 pins P87 to P80 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR8 and in PDR8 are valid only when the corresponding pin is designated in bits SGS3 to SGS0 in LPCR as a general I/O pin. Upon reset, PCR8 is initialized to H'00. PCR8 is a write-only register. All bits are read as 1. 175 8.9.3 Pin Functions Table 8-24 shows the port 8 pin functions. Table 8-24 Port 8 Pin Functions Pin P87/SEG32 to P84/SEG29 Pin Functions and Selection Method The pin function depends on bit PCR8n in PCR8 and bits SGS3 to SGS0 in LPCR. (n = 7 to 4) SGS3 to SGS0 PCR8n Pin function P83/SEG28 to P80/SEG25 0 000* 1 001*, 01** or 1*** * SEGn+25 output pin P8n input pin P8n output pin The pin function depends on bit PCR8n in PCR8 and bits SGS3 to SGS0 in LPCR. (n = 3 to 0) SGS3 to SGS0 PCR8n Pin function 0 000* or 0010 1 0011, 01** or 1*** * SEGn+25 output pin P8n input pin P8n output pin Note: * Don't care 8.9.4 Pin States Table 8-25 shows the port 8 pin states in each operating mode. Table 8-25 Port 8 Pin States Pins P87/SEG32 to P80/SEG25 Reset Sleep Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state 176 8.10 Port 9 8.10.1 Overview Port 9 is an 8-bit I/O port configured as shown in figure 8-9. P9 7 /SEG 40 /CL 1 P9 6 /SEG 39 /CL 2 P9 5 /SEG 38 /DO Port 9 P9 4 /SEG 37 /M P9 3 /SEG 36 P9 2 /SEG 35 P9 1 /SEG 34 P9 0 /SEG 33 Figure 8-9 Port 9 Pin Configuration 8.10.2 Register Configuration and Description Table 8-26 shows the port 9 register configuration. Table 8-26 Port 9 Registers Name Port data register 9 Port control register 9 Abbrev. PDR9 PCR9 R/W R/W W Initial Value H'00 H'00 Address H'FFDC H'FFEC 177 1. Bit Port data register 9 (PDR9) 7 P9 7 0 R/W 6 P9 6 0 R/W 5 P95 0 R/W 4 P9 4 0 R/W 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 P9 0 0 R/W Initial value Read/Write PDR9 is an 8-bit register that stores data for port 9 pins P97 to P90. If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read. Upon reset, PDR9 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 9 (PCR9) 7 PCR97 0 W 6 PCR96 0 W 5 PCR95 0 W 4 PCR94 0 W 3 PCR93 0 W 2 PCR92 0 W 1 PCR91 0 W 0 PCR90 0 W PCR9 is an 8-bit register for controlling whether each of the port 9 pins P97 to P90 functions as an input or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and in PDR9 are valid only when the corresponding pin is designated in bits SGS3 to SGS0 in LPCR as a general I/O pin. Upon reset, PCR9 is initialized to H'00. PCR9 is a write-only register. All bits are read as 1. 178 8.10.3 Pin Functions Table 8-27 shows the port 9 pin functions. Table 8-27 Port 9 Pin Functions Pin P97/SEG40/CL1 Pin Functions and Selection Method The pin function depends on bit PCR97 in PCR9, and bits SGX and SGS3 to SGS0 in LPCR. SGS3 to SGS0 SGX PCR97 Pin function P96/SEG39/CL2 0 0000 0 1 Not 0000 0 * * 1 * P97 input pin P97 output pin SEG40 output pin CL1 output pin The pin function depends on bit PCR96 in PCR9, and bits SGX and SGS3 to SGS0 in LPCR. SGS3 to SGS0 SGX PCR96 Pin function 0 0000 0 1 Not 0000 0 * * 1 * P96 input pin P96 output pin SEG39 output pin CL2 output pin P95/SEG38/DO The pin function depends on bit PCR95 in PCR9, and bits SGX and SGS3 to SGS0 in LPCR. SGS3 to SGS0 SGX PCR95 Pin function 0 0000 0 1 Not 0000 0 * * 1 * P95 input pin P95 output pin SEG38 output pin DO output pin P94/SEG37/M The pin function depends on bit PCR94 in PCR9, and bits SGX and SGS3 to SGS0 in LPCR. SGS3 to SGS0 SGX PCR94 Pin function 0 0000 0 1 Not 0000 0 * * 1 * M output pin P94 input pin P94 output pin SEG37 output pin Note: * Don't care 179 Table 8-27 Port 9 Pin Functions (cont) Pin 93/SEG36 to P90/SEG33 Pin Functions and Selection Method The pin function depends on bit PCR9n in PCR9 and bits SGS3 to SGS0 in LPCR. (n = 3 to 0) SGS3 to SGS0 PCR9n Pin function Note: * Don't care 0 0000 1 Not 0000 * SEGn+33 output pin P9n input pin P9n output pin 8.10.4 Pin States Table 8-28 shows the port 9 pin states in each operating mode. Table 8-28 Port 9 Pin States Pins P97/SEG40/CL1 P96/SEG39/CL2 P95/SEG38/DO P94/SEG37/M P93/SEG36 to P90/SEG33 Reset Sleep Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state 180 8.11 Port A 8.11.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8-10. PA 3 /COM 4 Port A PA 2 /COM 3 PA 1 /COM 2 PA 0 /COM 1 Figure 8-10 Port A Pin Configuration 8.11.2 Register Configuration and Description Table 8-29 shows the port A register configuration. Table 8-29 Port A Registers Name Port data register A Port control register A Abbrev. PDRA PCRA R/W R/W W Initial Value H'F0 H'F0 Address H'FFDD H'FFED 181 1. Bit Port data register A (PDRA) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PA 3 0 R/W 2 PA2 0 R/W 1 PA1 0 R/W 0 PA 0 0 R/W Initial value Read/Write PDRA is an 8-bit register that stores data for port A pins PA3 to PA0. If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read. Upon reset, PDRA is initialized to H'F0. 2. Bit Initial value Read/Write Port control register A (PCRA) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PCRA 3 0 W 2 PCRA 2 0 W 1 PCRA 1 0 W 0 PCRA 0 0 W PCRA is an 8-bit register for controlling whether each of the port A pins PA3 to PA0 functions as an input or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCRA and in PDRA are valid only when the corresponding pin is designated in LPCR as a general I/O pin. Upon reset, PCRA is initialized to H'F0. PCRA is a write-only register. All bits are read as 1. 182 8.11.3 Pin Functions Table 8-30 gives the port A pin functions. Table 8-30 Port A Pin Functions Pin PA3/COM4 Pin Functions and Selection Method The pin function depends on bit PCRA3 in PCRA and bits DTS1, DTS0, CMX, SGX, and SGS3 to SGS0 in LPCR. CMX DTS1,DTS0 SGX * ** 0 1 0 Not 11 * * ** 0 0 Not 11 1 * 1 1 Not 11 * Not 0000 * COM4 output pin 1 * 11 * SGS3 to SGS0 0000 Not 0000 0000 Not 0000 0000 PCRA3 Pin function PA2/COM3 0 1 0000 Not 0000 PA3 input pin PA3 output pin The pin function depends on bit PCRA2 in PCRA and bits DTS1, DTS0, CMX, SGX, and SGS3 to SGS0 in LPCR. CMX DTS1,DTS0 SGX * ** 0 0 * 0 00 or 01 1 * 1 00 or 01 1 * Not 0000 * COM3 output pin * Not 00 or 01 1 * 00 or 01 ** 1 * 0 SGS3 to SGS0 0000 Not 0000 0000 Not 0000 0000 PCRA2 Pin function PA1/COM2 0 1 0000 Not 0000 PA2 input pin PA2 output pin The pin function depends on bit PCRA1 in PCRA and bits DTS1, DTS0, CMX, SGX, and SGS3 to SGS0 in LPCR. CMX DTS1,DTS0 SGX * ** 0 1 0 00 * * ** 0 1 0 00 * 1 1 00 * Not 0000 * COM2 output pin * Not 00 1 * SGS3 to SGS0 0000 Not 0000 0000 Not 0000 0000 PCRA1 Pin function Note: * Don't care 0 1 0000 Not 0000 PA1 input pin PA1 output pin 183 Table 8-30 Port A Pin Functions (cont) Pin PA0/COM1 Pin Functions and Selection Method The pin function depends on bit PCRA0 in PCRA, and bits SGX and SGS3 to SGS0 in LPCR. SGS3 to SGS0 SGX PCRA0 Pin function Note: * Don't care 0 0000 0 1 0000 1 * COM1 output pin Not 0000 * PA0 input pin PA0 output pin 8.11.4 Pin States Table 8-31 shows the port A pin states in each operating mode. Table 8-31 Port A Pin States Pins PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state 184 8.12 Port B 8.12.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8-11. PB7 /AN 7 PB6 /AN 6 PB5 /AN 5 Port B PB4 /AN 4 PB3 /AN 3 PB2 /AN 2 PB1 /AN 1 PB0 /AN 0 Figure 8-11 Port B Pin Configuration 8.12.2 Register Configuration and Description Table 8-32 shows the port B register configuration. Table 8-32 Port B Register Name Port data register B Abbrev. PDRB R/W R Address H'FFDE Port Data Register B (PDRB) Bit 7 PB 7 Read/Write R 6 PB6 R 5 PB5 R 4 PB 4 R 3 PB3 R 2 PB2 R 1 PB1 R 0 PB 0 R Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. 185 8.13 Port C 8.13.1 Overview Port C is a 4-bit input-only port, configured as shown in figure 8-12. PC3 /AN 11 Port C PC2 /AN 10 PC1 /AN 9 PC0 /AN 8 Figure 8-12 Port C Pin Configuration 8.13.2 Register Configuration and Description Table 8-33 shows the port C register configuration. Table 8-33 Port C Register Name Port data register C Abbrev. PDRC R/W R Address H'FFDF Port Data Register C (PDRC) Bit 7 -- Read/Write -- 6 -- -- 5 -- -- 4 -- -- 3 PC3 R 2 PC2 R 1 PC1 R 0 PC 0 R Reading PDRC always gives the pin states. However, if a port C pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. 186 Section 9 Timers 9.1 Overview The H8/3834U Series provides five timers (timers A, B, C, F, and G) on-chip. Table 9-1 outlines the functions of timers A, B, C, F, and G. Table 9-1 Timer Functions Name Functions Internal Clock o/8 to o/8192 (8 choices) Event Input Pin -- Waveform Output Pin -- -- Remarks Timer A * 8-bit timer * Interval timer * 8-bit timer * Time base * 8-bit timer * clock output Timer B * 8-bit timer * Interval timer * Event counter Timer C * 8-bit timer * Interval timer * Event counter * Choice of up- or downcounting Timer F oW/128 -- (choice of 4 overflow periods) o/4 to o/32, oW/4 to oW/32 (8 choices) o/4 to o/8192 (7 choices) o/4 to o/8192, oW/4 (7 choices) -- TMOW TMIB -- TMIC -- Counting direction can be controlled by software or hardware * 16-bit timer o/2 to o/32 * Event counter (4 choices) * Can be used as two independent 8-bit timers * Output compare TMIF TMOFL TMOFH Timer G * 8-bit timer * Input capture * Interval timer o/2 to o/64, oW/2 TMIG (4 choices) -- * Counter clear designation possible * Built-in noise canceller circuit for input capture 187 9.2 Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. 1. Features Features of timer A are given below. * Choice of eight internal clock sources (o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8). Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal oscillator). An interrupt is requested when the counter overflows. Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or 4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4. * * * 188 2. Block diagram Figure 9-2-1 shows a block diagram of timer A. oW 1/4 oW/4 PSW TMA oW /128 TCA / 8* / 64 * /128 * /256 * TMOW o/32 o/16 o/8 o/4 o o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8 PSS IRRTA Notation: TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag (interrupt request register 1) PSW: Prescaler W PSS: Prescaler S Note: Can be selected only when the prescaler W output (o W /128) is used as the TCA input clock. Figure 9-2-1 Block Diagram of Timer A 3. Pin configuration Table 9-2-1 shows the timer A pin configuration. Table 9-2-1 Pin Configuration Name Clock output Abbrev. TMOW I/O Output Function Output of waveform generated by timer A output circuit 189 Internal data bus oW /32 oW /16 oW /8 oW /4 4. Register configuration Table 9-2-2 shows the register configuration of timer A. Table 9-2-2 Timer A Registers Name Timer mode register A Timer counter A Abbrev. TMA TCA R/W R/W R Initial Value H'10 H'00 Address H'FFB0 H'FFB1 9.2.2 Register Descriptions 1. Bit Initial value Read/Write Timer mode register A (TMA) 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. Upon reset, TMA is initialized to H'10. Bits 7 to 5: Clock output select (TMA7 to TMA5) Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. Bit 7 TMA7 0 Bit 6 TMA6 0 Bit 5 TMA5 0 1 1 0 1 1 0 0 1 1 0 1 Clock Output o/32 o/16 o/8 o/4 oW/32 oW/16 oW/8 oW/4 (initial value) 190 Bit 4: Reserved bit Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 TMA3 0 Bit 2 TMA2 0 Bit 1 TMA1 0 Bit 0 TMA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Prescaler and Divider Ratio or Overflow Period PSS, o/8192 PSS, o/4096 PSS, o/2048 PSS, o/512 PSS, o/256 PSS, o/128 PSS, o/32 PSS, o/8 PSW, 1 s PSW, 0.5 s PSW, 0.25 s PSW, 0.03125 s PSW and TCA are reset Clock time base (initial value) Function Interval timer 191 2. Bit Timer counter A (TCA) 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R Initial value Read/Write TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Upon reset, TCA is initialized to H'00. 9.2.3 Timer Operation 1. Interval timer operation When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. Note: * For details on interrupts, see 3.3, Interrupts. 192 2. Real-time clock time base operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00. 3. Clock output Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. 9.2.4 Timer A Operation States Table 9-2-3 summarizes the timer A operation states. Table 9-2-3 Timer A Operation States Operation Mode TCA Interval Clock time base TMA Reset Active Reset Reset Reset Sleep Watch Subactive Halted Subsleep Halted Standby Halted Functions Functions Halted Functions Functions Functions Functions Functions Halted Functions Retained Retained Functions Retained Retained Note: When real-time clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/o (s) in the count cycle. 193 9.3 Timer B 9.3.1 Overview Timer B is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer B are given below. * Choice of seven internal clock sources (o/8192, o/2048, o/512, o/256, o/64, o/16, o/4) or an external clock (can be used to count external events). An interrupt is requested when the counter overflows. Block Diagram * 2. Figure 9-3-1 shows a block diagram of timer B. TMB o PSS TCB TMIB TLB Notation: TMB: Timer mode register B TCB: Timer counter B TLB: Timer load register B IRRTB: Timer B overflow interrupt request flag PSS: Prescaler S Figure 9-3-1 Block Diagram of Timer B 194 Internal data bus IRRTB 3. Pin configuration Table 9-3-1 shows the timer B pin configuration. Table 9-3-1 Pin Configuration Name Timer B event input Abbrev. TMIB I/O Input Function Event input to TCB 4. Register configuration Table 9-3-2 shows the register configuration of timer B. Table 9-3-2 Timer B Registers Name Timer mode register B Timer counter B Timer load register B Abbrev. TMB TCB TLB R/W R/W R W Initial Value H'78 H'00 H'00 Address H'FFB2 H'FFB3 H'FFB3 9.3.2 Register Descriptions 1. Bit Initial value Read/Write Timer mode register B (TMB) 7 TMB7 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 TMB2 0 R/W 1 TMB1 0 R/W 0 TMB0 0 R/W TMB is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TMB is initialized to H'78. Bit 7: Auto-reload function select (TMB7) Bit 7 selects whether timer B is used as an interval timer or auto-reload timer. Bit 7 TMB7 0 1 Description Interval timer function selected Auto-reload function selected (initial value) 195 Bits 6 to 3: Reserved bits Bits 6 to 3 are reserved; they always read 1, and cannot be modified. Bits 2 to 0: Clock select (TMB2 to TMB0) Bits 2 to 0 select the clock input to TCB. For external event counting, either the rising or falling edge can be selected. Bit 2 TMB2 0 0 0 0 1 1 1 1 Bit 1 TMB1 0 0 1 1 0 0 1 1 Bit 0 TMB0 0 1 0 1 0 1 0 1 Description Internal clock: o/8192 Internal clock: o/2048 Internal clock: o/512 Internal clock: o/256 Internal clock: o/64 Internal clock: o/16 Internal clock: o/4 External event (TMIB): rising or falling edge* (initial value) Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select register (IEGR). See 3.3.2, Interrupt Control Registers, for details on the IRQ edge select register. Be sure to set bit IRQ1 in port mode register 1 (PMR1) to 1 before setting bits TMB2 to TMB0 to 111. 2. Bit Timer counter B (TCB) 7 TCB7 0 R 6 TCB6 0 R 5 TCB5 0 R 4 TCB4 0 R 3 TCB3 0 R 2 TCB2 0 R 1 TCB1 0 R 0 TCB0 0 R Initial value Read/Write TCB is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode register B (TMB). TCB values can be read by the CPU at any time. When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt request register 2 (IRR2) is set to 1. TCB is allocated to the same address as timer load register B (TLB). Upon reset, TCB is initialized to H'00. 196 3. Bit Timer load register B (TLB) 7 TLB7 0 W 6 TLB6 0 W 5 TLB5 0 W 4 TLB4 0 W 3 TLB3 0 W 2 TLB2 0 W 1 TLB1 0 W 0 TLB0 0 W Initial value Read/Write TLB is an 8-bit write-only register for setting the reload value of timer counter B. When a reload value is set in TLB, the same value is loaded into timer counter B (TCB) as well, and TCB starts counting up from that value. When TCB overflows during operation in autoreload mode, the TLB value is loaded into TCB. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLB as to TCB. Upon reset, TLB is initialized to H'00. 9.3.3 Timer Operation 1. Interval timer operation When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit interval timer. Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer B is selected from seven internal clock signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by bits TMB2 to TMB0 of TMB. After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow, setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If IENTB = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow, TCB returns to H'00 and starts counting up again. During interval timer operation (TMB7 = 0), when a value is set in timer load register B (TLB), the same value is set in TCB. Note: * For details on interrupts, see 3.3, Interrupts. 197 2. Auto-reload timer operation Setting bit TMB7 in TMB to 1 causes timer B to function as an 8-bit auto-reload timer. When a reload value is set in TLB, the same value is loaded into TCB, becoming the value from which TCB starts its count. After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow. The TLB value is then loaded into TCB, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB value. The clock sources and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMB7 = 1), when a new value is set in TLB, the TLB value is also set in TCB. 3. Event counter operation Timer B can operate as an event counter, counting rising or falling edges of an external event signal input at pin TMIB. External event counting is selected by setting bits TMB2 to TMB0 in timer mode register B to all 1s (111). When timer B is used to count external event input, bit IRQ1 in port mode register 1 (PMR1) should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be cleared to 0 to disable IRQ1 interrupt requests. 9.3.4 Timer B Operation States Table 9-3-3 summarizes the timer B operation states. Table 9-3-3 Timer B Operation States Operation Mode TCB Interval Auto reload TMB Reset Reset Reset Reset Active Functions Functions Functions Sleep Functions Functions Retained Watch Halted Halted Retained Subactive Halted Halted Subsleep Halted Halted Standby Halted Halted Retained Retained Retained 198 9.4 Timer C 9.4.1 Overview Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features The main features of timer C are given below. * Choice of seven internal clock sources (o/8192, o/2048, o/512, o/64, o/16, o/4, oW/4) or an external clock (can be used to count external events). An interrupt is requested when the counter overflows. Can be switched between up- and down-counting by software or hardware. When oW/4 is selected as the internal clock source, or when an external clock is selected, timer C can function in subactive mode and subsleep mode. * * * 199 2. Block diagram Figure 9-4-1 shows a block diagram of timer C. TMC Internal data bus IRRTC UD o TMIC oW/4 TLC PSS TCC Notation: TMC: TCC: TLC: IRRTC: PSS: Timer mode register C Timer counter C Timer load register C Timer C overflow interrupt request flag Prescaler S Figure 9-4-1 Block Diagram of Timer C 3. Pin configuration Table 9-4-1 shows the timer C pin configuration. Table 9-4-1 Pin Configuration Name Timer C event input Timer C up/down control Abbrev. TMIC UD I/O Input Input Function Event input to TCC Selection of counting direction 200 4. Register configuration Table 9-4-2 shows the register configuration of timer C. Table 9-4-2 Timer C Registers Name Timer mode register C Timer counter C Timer load register C Abbrev. TMC TCC TLC R/W R/W R W Initial Value H'18 H'00 H'00 Address H'FFB4 H'FFB5 H'FFB5 9.4.2 Register Descriptions 1. Bit Initial value Read/Write Timer mode register C (TMC) 7 TMC7 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W TMC is an 8-bit read/write register for selecting the auto-reload function, counting direction, and input clock. Upon reset, TMC is initialized to H'18. Bit 7: Auto-reload function select (TMC7) Bit 7 selects whether timer C is used as an interval timer or auto-reload timer. Bit 7 TMC7 0 1 Description Interval timer function selected Auto-reload function selected (initial value) 201 Bits 6 and 5: Counter up/down control (TMC6 and TMC5) These bits select the counting direction of timer counter C (TCC), or allow hardware to control the counting direction using pin UD. Bit 6 TMC6 0 0 1 Bit 5 TMC5 0 1 * Description TCC is an up-counter TCC is a down-counter TCC up/down control is determined by input at pin UD. TCC is a downcounter if the UD input is high, and an up-counter if the UD input is low. (initial value) Note: * Don't care Bits 4 and 3: Reserved bits Bits 4 and 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0: Clock select (TMC2 to TMC0) Bits 2 to 0 select the clock input to TCC. For external clock counting, either the rising or falling edge can be selected. Bit 2 TMC2 0 0 0 0 1 1 1 1 Bit 1 TMC1 0 0 1 1 0 0 1 1 Bit 0 TMC0 0 1 0 1 0 1 0 1 Description Internal clock: o/8192 Internal clock: o/2048 Internal clock: o/512 Internal clock: o/64 Internal clock: o/16 Internal clock: o/4 Internal clock: oW/4 External event (TMIC): rising or falling edge* (initial value) Note: * The edge of the external event signal is selected by bit IEG2 in the IRQ edge select register (IEGR). See 3.3.2, Interrupt Control Registers, for details on the IRQ edge select register. Be sure to set bit IRQ2 in port mode register 1 (PMR1) to 1 before setting bits TMC2 to TMC0 to 111. 202 2. Bit Timer counter C (TCC) 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R 2 TCC2 0 R 1 TCC1 0 R 0 TCC0 0 R Initial value Read/Write TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time. When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1. TCC is allocated to the same address as timer load register C (TLC). Upon reset, TCC is initialized to H'00. 3. Bit Initial value Read/Write Timer load register C (TLC) 7 TLC7 0 W 6 TLC6 0 W 5 TLC5 0 W 4 TLC4 0 W 3 TLC3 0 W 2 TLC2 0 W 1 TLC1 0 W 0 TLC0 0 W TLC is an 8-bit write-only register for setting the reload value of TCC. When a reload value is set in TLC, the same value is loaded into timer counter C (TCC) as well, and TCC starts counting up or down from that value. When TCC overflows or underflows during operation in auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow and underflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLC as to TCC. Upon reset, TLC is initialized to H'00. 203 9.4.3 Timer Operation 1. Interval timer operation When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, timer counter C (TCC) is initialized to H'00 and TMC to H'18, so counting and interval timing resume immediately. The clock input to timer C is selected from seven internal clock signals output by prescalers S and W, or an external clock input at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC. Either software or hardware can control whether TCC counts up or down. The selection is made by TMC bits TMC6 and TMC5. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow or underflow, TCC returns to H'00 or H'FF and starts counting up or down again. During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: * For details on interrupts, see 3.3, Interrupts. 2. Auto-reload timer operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow). The TLC value is then loaded TCC, and the count continues from that value. The overflow (underflow) period can be set within a range from 1 to 256 input clocks, depending on the TLC value. 204 The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in TCC. 3. Event counter operation Timer C can operate as an event counter, counting an event signal input at pin TMIC. External event counting is selected by setting TMC bits TMC2 to TMC0 to all 1s (111). TCC counts up or down at the rising or falling edge of the input at pin TMIC. When timer C is used to count external event inputs, bit IRQ2 in port mode register 1 (PMR1) should be set to 1, and bit IEN2 in interrupt enable register 1 (IENR1) should be cleared to 0 to disable IRQ2 interrupt requests. 4. TCC up/down control by hardware The counting direction of timer C can be controlled by input at pin UD. When bit TMC6 in TMC is set to 1, high-level input at the UD pin selects down-counting, while low-level input selects upcounting. When using input at pin UD for this control function, set the UD bit in port mode register 2 (PMR2) to 1. 9.4.4 Timer C Operation States Table 9-4-3 summarizes the timer C operation states. Table 9-4-3 Timer C Operation States Operation Mode TCC Interval Reset Active Sleep Watch Subactive Functions/ Halted* Functions/ Halted* Functions Subsleep Standby Reset Functions Functions Halted Functions/ Halted Halted* Functions/ Halted Halted* Retained Retained TCC Auto reload Reset Functions Functions Halted TMC Reset Functions Retained Retained Note: When oW/4 is selected as the internal clock of TCC in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/o (s) in the count cycle. * When timer C is operated in subactive mode or subsleep mode, either an external clock or the oW/4 internal clock must be selected. The counter will not operate in these modes if another clock is selected. If the internal oW/4 clock is selected when oW/8 is being used as the subclock oSUB, the lower 2 bits of the counter will operate on the same cycle, with the least significant bit not being counted. 205 9.5 Timer F 9.5.1 Overview Timer F is a 16-bit timer with an output compare function. Compare match signals can be used to reset the counter, request an interrupt, or toggle the output. Timer F can also be used for external event counting, and can operate as two independent 8-bit timers, timer FH and timer FL. 1. Features Features of timer F are given below. * * * * * Choice of four internal clock sources (o/32, o/16, o/4, o/2) or an external clock (can be used as an external event counter). Output from pin TMOFH is toggled by one compare match signal (the initial value of the toggle output can be set). Counter can be reset by the compare match signal. Two interrupt sources: counter overflow and compare match. Can operate as two independent 8-bit timers (timer FH and timer FL) in 8-bit mode. Timer FH -- 8-bit timer (clocked by timer FL overflow signals when timer F operates as a 16-bit timer). -- Choice of four internal clocks (o/32, o/16, o/4, o/2). -- Output from pin TMOFH is toggled by one compare match signal (the initial value of the toggle output can be set). -- Counter can be reset by the compare match signal. -- Two interrupt sources: counter overflow and compare match. Timer FL -- 8-bit timer/event counter -- Choice of four internal clocks (o/32, o/16, o/4, o/2) or event input at pin TMIF. -- Output from pin TMOFL is toggled by one compare match signal (the initial value of the toggle output can be set). -- Counter can be reset by the compare match signal. -- Two interrupt sources: counter overflow and compare match. 206 2. Block diagram Figure 9-5-1 shows a block diagram of timer F. o PSS IRRTFL TCRF TMIF TMOFL Toggle circuit TCFL Compare circuit Internal data bus Match IRRTFH OCRFL TCFH Toggle circuit TMOFH Compare circuit OCRFH TCSRF Notation: TCRF: TCSRF: TCFH: TCFL: OCRFH: OCRFL: IRRTFH: IRRTFL: PSS: Timer control register F Timer control status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S Figure 9-5-1 Block Diagram of Timer F 207 3. Pin configuration Table 9-5-1 shows the timer F pin configuration. Table 9-5-1 Pin Configuration Name Timer F event input Timer FH output Timer FL output Abbrev. TMIF TMOFH TMOFL I/O Input Output Output Function Event input to TCFL Timer FH output Timer FL output 4. Register configuration Table 9-5-2 shows the register configuration of timer F. Table 9-5-2 Timer F Registers Name Timer control register F Timer control/status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Abbrev. TCRF TCSRF TCFH TCFL OCRFH OCRFL R/W W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'FF H'FF Address H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB 9.5.2 Register Descriptions 1. 16-bit timer counter (TCF) 8-bit timer counter (TCFH) 8-bit timer counter (TCFL) TCF Bit Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL 208 TCF is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, TCFH and TCFL. TCF can be used as a 16-bit counter, with TCFH as the upper 8 bits and TCFL as the lower 8 bits of the counter, or TCFH and TCFL can be used as independent 8-bit counters. TCFH and TCFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP). For details see 9.5.3, Interface with the CPU. Upon reset, TCFH and TCFL are each initialized to H'00. * 16-bit mode (TCF) 16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The TCF input clock is selected by TCRF bits CKSL2 to CKSL0. Timer control status register F (TCSRF) can be set so that counter TCF will be cleared by compare match. When TCF overflows from H'FFFF to H'0000, the overflow flag (OVFH) in TCSRF is set to 1. If bit OVIEH in TCSRF is set to 1 when an overflow occurs, bit IRRTFH in interrupt request register 2 (IRR2) will be set to 1; and if bit IENTFH in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt will be requested. * 8-bit mode (TCFH, TCFL) When bit CKSH2 in timer control register F (TCRF) is set to 1, timer F functions as two separate 8-bit counters, TCFH and TCFL. The TCFH (TCFL) input clock is selected by TCRF bits CKSH2 to CKSH0 (CKSL2 to CKSL0). TCFH (TCFL) can be cleared by a compare match signal. This designation is made in bit CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, the overflow flag OVFH (OVFL) in TCSRF is set to 1. If bit OVIEH (OVIEL) in TCSRF is set to 1 when an overflow occurs, bit IRRTFH (IRRTHL) in interrupt request register 2 (IRR2) will be set to 1; and if bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt will be requested. 209 2. 16-bit output compare register (OCRF) 8-bit output compare register (OCRFH) 8-bit output compare register (OCRFL) OCRF Bit Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRFH OCRFL OCRF is a 16-bit read/write output compare register consisting of two 8-bit read/write registers OCRFH and OCRFL. It can be used as a 16-bit output compare register, with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits of the register, or OCRFH and OCRFL can be used as independent 8-bit registers. OCRFH and OCRFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP). For details see 9.5.3, Interface with the CPU. Upon reset, OCRFH and OCRFL are each initialized to H'FF. * 16-bit mode (OCRF) 16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The OCRF contents are always compared with the 16-bit timer counter (TCF). When the contents match, the compare match flag (CMFH) in TCSRF is set to 1. Also, IRRTFH in interrupt request register 2 (IRR2) is set to 1. If bit IENTFH in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Output for pin TMOFH can be toggled by compare match. The output level can also be set to high or low by bit TOLH of timer control register F (TCRF). * 8-bit mode (OCRFH, OCRFL) Setting bit CKSH2 in TCRF to 1 results in two independent output compare registers, OCRFH and OCRFL. The OCRFH contents are always compared with TCFH, and the OCRFL contents are always compared with TCFL. When the contents match, the compare match flag (CMFH or CMFL) in TCSRF is set to 1. Also, bit IRRTFH (IRRTFL) in interrupt request register 2 (IRR2) set to 1. If bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1 at this time, a CPU interrupt is requested. 210 The output at pin TMOFH (TMOFL) can be toggled by compare match. The output level can also be set to high or low by bit TOLH (TOLL) of the timer control register (TCRF). 3. Bit Initial value Read/Write Timer control register F (TCRF) 7 TOLH 0 W 6 CKSH2 0 W 5 CKSH1 0 W 4 CKSH0 0 W 3 TOLL 0 W 2 CKSL2 0 W 1 CKSL1 0 W 0 CKSL0 0 W TCRF is an 8-bit write-only register. It is used to switch between 16-bit mode and 8-bit mode, to select among four internal clocks and an external clock, and to select the output level at pins TMOFH and TMOFL. Upon reset, TCRF is initialized to H'00. Bit 7: Toggle output level H (TOLH) Bit 7 sets the output level at pin TMOFH. The setting goes into effect immediately after this bit is written. Bit 7 TOLH 0 1 Description Low level High level (initial value) Bits 6 to 4: Clock select H (CKSH2 to CKSH0) Bits 6 to 4 select the input to TCFH from four internal clock signals or the overflow of TCFL. Bit 6 CKSH2 0 1 1 1 1 Bit 5 CKSH1 * 0 0 1 1 Bit 4 CKSH0 * 0 1 0 1 Description 16-bit mode selected. TCFL overflow signals are counted. Internal clock: o/32 Internal clock: o/16 Internal clock: o/4 Internal clock: o/2 (initial value) Note: * Don't care 211 Bit 3: Toggle output level L (TOLL) Bit 3 sets the output level at pin TMOFL. The setting goes into effect immediately after this bit is written. Bit 3 TOLL 0 1 Description Low level High level (initial value) Bits 2 to 0: Clock select L (CKSL2 to CKSL0) Bits 2 to 0 select the input to TCFL from four internal clock signals or external event input. Bit 2 CKSL2 0 1 1 1 1 Bit 1 CKSL1 * 0 0 1 1 Bit 0 CKSL0 * 0 1 0 1 Description External event (TMIF). Rising or falling edge is counted (see note). Internal clock: o/32 Internal clock: o/16 Internal clock: o/4 Internal clock: o/2 (initial value) * Don't care Note: The edge of the external event signal is selected by bit IEG3 in the IRQ edge select register (IEGR). See 3.3.2, Interrupt Control Registers, for details on the IRQ edge select register. Note that switching the TMIF pin function by changing bit IRQ3 in port mode register 1 (PMR1) from 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer F counter to be incremented. 4. Timer control/status register F (TCSRF) 7 OVFH 0 R/W* 6 CMFH 0 R/W* 5 OVIEH 0 R/W 4 CCLRH 0 R/W 3 OVFL 0 R/W* 2 CMFL 0 R/W* 1 OVIEL 0 R/W 0 CCLRL 0 R/W Bit Initial value Read/Write Note: * Only 0 can be written, to clear flag. TCSRF is an 8-bit read/write register. It is used for counter clear selection, overflow and compare match indication, and enabling of interrupts caused by timer overflow. Upon reset, TCSRF is initialized to H'00. 212 Bit 7: Timer overflow flag H (OVFH) Bit 7 is a status flag indicating TCFH overflow (H'FF to H'00). This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 OVFH 0 1 Description Clearing conditions: After reading OVFH = 1, cleared by writing 0 to OVFH Setting conditions: Set when the value of TCFH goes from H'FF to H'00 (initial value) Bit 6: Compare match flag H (CMFH) Bit 6 is a status flag indicating a compare match between TCFH and OCRFH. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 CMFH 0 1 Description Clearing conditions: After reading CMFH = 1, cleared by writing 0 to CMFH Setting conditions: Set when the TCFH value matches OCRFH value (initial value) Bit 5: Timer overflow interrupt enable H (OVIEH) Bit 5 enables or disables TCFH overflow interrupts. Bit 5 OVIEH 0 1 Description TCFH overflow interrupt disabled TCFH overflow interrupt enabled (initial value) 213 Bit 4: Counter clear H (CCLRH) In 16-bit mode, bit 4 selects whether or not TCF is cleared when a compare match occurs between TCF and OCRF. In 8-bit mode, bit 4 selects whether or not TCFH is cleared when a compare match occurs between TCFH and OCRFH. Bit 4 CCLRH 0 1 Description 16-bit mode: TCF clearing by compare match disabled 8-bit mode: TCFH clearing by compare match disabled 16-bit mode: TCF clearing by compare match enabled 8-bit mode: TCFH clearing by compare match enabled (initial value) Bit 3: Timer overflow flag L (OVFL) Bit 3 is a status flag indicating TCFL overflow (H'FF to H'00). This flag is set by hardware and cleared by software. It cannot be set by software. Bit 3 OVFL 0 1 Description Clearing conditions: After reading OVFL = 1, cleared by writing 0 to OVFL Setting conditions: Set when the value of TCFL goes from H'FF to H'00 (initial value) Bit 2: Compare match flag L (CMFL) Bit 2 is a status flag indicating a compare match between TCFL and OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 CMFL 0 1 Description Clearing conditions: After reading CMFL = 1, cleared by writing 0 to CMFL Setting conditions: Set when the TCFL value matches the OCRFL value (initial value) 214 Bit 1: Timer overflow interrupt enable L (OVIEL) Bit 1 enables or disables TCFL overflow interrupts. Bit 1 OVIEL 0 1 Description TCFL overflow interrupt disabled TCFL overflow interrupt enabled (initial value) Bit 0: Counter clear L (CCLRL) Bit 0 selects whether or not TCFL is cleared when a compare match occurs between TCFL and OCRFL. Bit 0 CCLRL 0 1 Description TCFL clearing by compare match disabled TCFL clearing by compare match enabled (initial value) 9.5.3 Interface with the CPU TCF and OCRF are 16-bit read/write registers, whereas the data bus between the CPU and on-chip peripheral modules has an 8-bit width. For this reason, when the CPU accesses TCF or OCRF, it makes use of an 8-bit temporary register (TEMP). In 16-bit mode, when reading or writing TCF or writing OCRF, always use two consecutive byte size MOV instructions, and always access the upper byte first. Data will not be transferred properly if only the upper byte or only the lower byte is accessed. In 8-bit mode there is no such restriction on the order of access. * Write access When the upper byte is written, the upper-byte data is loaded into the TEMP register. Next when the lower byte is written, the data in TEMP goes to the upper byte of the register, and the lowerbyte data goes directly to the lower byte of the register. Figure 9-5-2 shows a TCF write operation when H'AA55 is written to TCF. 215 * Read access When the upper byte of TCF is read, the upper-byte data is sent directly to the CPU, and the lower byte is loaded into TEMP. Next when the lower byte is read, the lower byte in TEMP is sent to the CPU. When the upper byte of OCRF is read, the upper-byte data is sent directly to the CPU. Next when the lower byte is read, the lower-byte data is sent directly to the CPU. Figure 9-5-3 shows a TCF read operation when H'AAFF is read from TCF. 216 Upper byte write Bus interface CPU (H'AA) Internal data bus TEMP (H'AA) TCFH ( ) Lower byte write Bus interface TCFL ( ) CPU (H'55) Internal data bus TEMP (H'AA) TCFH (H'AA) TCFL (H'55) Figure 9-5-2 TCF Write Operation (CPU TCF) 217 Upper byte read Bus interface CPU (H'AA) Internal data bus TEMP (H'FF) TCFH (H'AA) Lower byte read Bus interface TCFL (H'FF) CPU (H'FF) Internal data bus TEMP (H'FF) TCFH (AB) * Note: * Becomes H'AB00 if counter is incremented once. TCFL (00) * Figure 9-5-3 TCF Read Operation (TCF CPU) 218 9.5.4 Timer Operation Timer F is a 16-bit timer/counter that increments with each input clock. When the value set in output compare register F matches the count in timer F, the timer can be cleared, an interrupt can be requested, and the port output can be toggled. Timer F can also be used as two independent 8-bit timers. 1. Timer F operation Timer F can operate in either 16-bit timer mode or 8-bit timer mode. These modes are described below. * 16-bit timer mode Timer F operates in 16-bit timer mode when the CKSH2 bit in timer control register F (TCRF) is cleared to 0. A reset initializes timer counter F (TCF) to H'0000, output compare register F (OCRF) to H'FFFF, and timer control register F (TCRF) and timer control status register F (TCSRF) to H'00. Timer F begins counting external event input signals (TMIF). The edge of the external event signal is selected by the IEG3 bit in the IRQ edge select register (IEGR). Instead of counting external events, timer F can be switched by bits CKSL2 to CKSL0 in TCRF to count one of four internal clocks output by prescaler S. TCF is continuously compared with the contents of OCRF. When these two values match, the CMFH bit in TCSRF is set to 1. At this time if IENTFH of IENR2 is 1, a CPU interrupt is requested and the output at pin TMOFH is toggled. If the CCLRH bit in TCSRF is 1, timer F is cleared. The output at pin TMOFH can also be set by the TOLH bit in TCRF. If timer F overflows (from H'FFFF to H'0000), the OVFH bit in TCSRF is set to 1. At this time, if the OVIEH bit in TCSRF and the IENTFH bit in IENR2 are both 1, a CPU interrupt is requested. 219 * 8-bit timer mode When the CKSH2 bit in TCRF is set to 1, timer F operates as two independent 8-bit timers, TCFH and TCFL. The input clock of TCFH/TCFL is selected by bits CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When TCFH/TCFL and the contents of OCRFH/OCRFL match, the CMFH/CMFL bit in TCSRF is set to 1. If the IENTFH/IENTFL bit in IENR2 is 1, a CPU interrupt is requested and the output at pin TMOFH/TMOFL is toggled. If the CCLRH/CCLRL bit in TCRF is 1, TCFH/TCFL is cleared. The output at pin TMOFH/TMOFL can also be set by the TOLH/TOLL bit in TCRF. When TCFH/TCFL overflows from H'FF to H'00, the OVFH/OVFL bit in TCSRF is set to 1. At this time, if the OVIEH/OVIEL bit in TCSRF and the IENTFH/IENTFL bit in IENR2 are both 1, a CPU interrupt is requested. 2. TCF count timing TCF is incremented by each pulse of the input clock (internal or external clock). * Internal clock The settings of bits CKSH2 to CKSH0 or bits CKSL2 to CKSL0 in TCRF select one of four internal clock signals divided from the system clock (o), namely, o/32, o/16, o/4, or o/2. * External clock External clock input is selected by clearing bit CKSL2 to 0 in TCRF. Either rising or falling edges of the clock input can be counted. The edge is selected by bit IEG3 in IEGR. An external clock pulse width of at least two system clock cycles (o) is necessary; otherwise the counter will not operate properly. 220 3. TMOFH and TMOFL output timing The outputs at pins TMOFH and TMOFL are the values set in bits TOLH and TOLL in TCRF. When a compare match occurs, the output value is inverted. Figure 9-5-4 shows the output timing. o TMIF (when IEG3 = 1) Count input clock TCF N N+1 N N+1 OCRF N N Compare match signal TMOFH, TMOFL Figure 9-5-4 TMOFH, TMOFL Output Timing 4. TCF clear timing TCF can be cleared at compare match with OCRF. 5. Timer overflow flag (OVF) set timing OVF is set to 1 when TCF overflows (goes from H'FFFF to H'0000). 6. Compare match flag set timing The compare match flags (CMFH or CMFL) are set to 1 when a compare match occurs between TCF and OCRF. A compare match signal is generated in the final state in which the values match (when TCF changes from the matching count value to the next value). When TCF and OCRF match, a compare match signal is not generated until the next counter clock pulse. 221 7. Timer F operation states Table 9-5-3 summarizes the timer F operation states. Table 9-5-3 Timer F Operation States Operation Mode TCF OCRF TCRF TCSRF Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Sleep Functions Retained Retained Retained Watch Halted Retained Retained Retained Subactive Halted Retained Retained Retained Subsleep Halted Retained Retained Retained Standby Halted Retained Retained Retained 9.5.5 Application Notes The following conflicts can arise in timer F operation. 1. 16-bit timer mode The output at pin TMOFH toggles when all 16 bits match and a compare match signal is generated. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH. The TMOFL output in 16-bit mode is indeterminate, so this output should not be used. Use the pin as a general input or output port. If an OCRFL write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated; bit CMFL is set when the setting conditions are met for the lower 8 bits. The overflow flag (OVFH) is set when TCF overflows; bit OVFL is set if the setting conditions are met when the lower 8 bits overflow. If a write to TCFL occurs at the same time as an overflow signal, the overflow signal is not output. 222 2. 8-bit timer mode TCFH and OCRFH The output at pin TMOFH toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH. If an OCRFH write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write occurs at the same time as an overflow signal, the overflow signal is not output. TCFL and OCRFL The output at pin TMOFL toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLL will be output at pin TMOFL. If an OCRFL write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. If a TCFL write occurs at the same time as an overflow signal, the overflow signal is not output. 223 9.6 Timer G 9.6.1 Overview Timer G is an 8-bit timer, with input capture functions for separately capturing the rising edge and falling edge of pulses input at the input capture pin (input capture input signal). Timer G has a built-in noise canceller circuit that can eliminate high-frequency noise from the input capture signal, enabling accurate measurement of its duty cycle. When timer G is not used for input capture, it functions as an 8-bit interval timer. 1. Features Features of timer G are given below. * * Choice of four internal clock sources (o/64, o/32, o/2, oW/2) Input capture function Separate input capture registers are provided for the rising and falling edges. * Counter overflow detection Can detect whether overflow occurred when the input capture signal was high or low. * Choice of counter clear triggers The counter can be cleared at the rising edge, falling edge, or both edges of the input capture signal. * Two interrupt sources Interrupts can be requested by input capture and by overflow. For input capture, the rising or falling edge can be selected. * Built-in noise-canceller circuit The noise canceller circuit can eliminate high-frequency noise in the input capture signal. * Operates in subactive and subsleep modes When oW/2 is selected as the internal clock source, timer G can operate in the subactive and subsleep modes. 224 2. Block diagram Figure 9-6-1 shows a block diagram of timer G. o PSS TMG Level sense circuit ICRGF Internal data bus IRRTG Notation: TMG: Timer mode register G TCG: Timer counter G ICRGF: Input capture register GF ICRGR: Input capture register GR IRRTG: Timer G interrupt request flag NCS: Noise canceller select PSS: Prescaler S o W /2 TMIG Noise canceller circuit Edge sense circuit TCG NCS ICRGR Figure 9-6-1 Block Diagram of Timer G 3. Pin configuration Table 9-6-1 shows the timer G pin configuration. Table 9-6-1 Pin Configuration Name Timer G capture input Abbrev. TMIG I/O Input Function Timer G capture input 225 4. Register configuration Table 9-6-2 shows the register configuration of timer G. Table 9-6-2 Timer G Registers Name Timer mode register G Timer counter G Input capture register GF Input capture register GR Abbrev. TMG TCG ICRGF ICRGR R/W R/W -- R R Initial Value H'00 H'00 H'00 H'00 Address H'FFBC -- H'FFBD H'FFBE 9.6.2 Register Descriptions 1. Bit Initial value Read/Write Timer counter G (TCG) 7 TCG7 0 -- 6 TCG6 0 -- 5 TCG5 0 -- 4 TCG4 0 -- 3 TCG3 0 -- 2 TCG2 0 -- 1 TCG1 0 -- 0 TCG0 0 -- Timer counter G (TCG) is an 8-bit up-counter which is incremented by an input clock. The input clock signal is selected by bits CKS1 and CKS0 in timer mode register G (TMG). To use TCG as an input capture timer, set bit TMIG to 1 in PMR1; to use TCG as an interval timer, clear bit TMIG to 0.* When TCG is used as an input capture timer, the TCG value can be cleared at the rising edge, falling edge, or both edges of the input capture signal, depending on settings in TMG. When TCG overflows (goes from H'FF to H'00), if the timer overflow interrupt enable bit (OVIE) is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on interrupts are given in 3.3, Interrupts. TCG cannot be read or written by the CPU. Upon reset, TCG is initialized to H'00. Note: * An input capture signal may be generated when TMIG is rewritten. 226 2. Bit Input capture register GF (ICRGF) 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write ICRGF is an 8-bit read-only register. When the falling edge of the input capture signal is detected, the TCG value at that time is transferred to ICRGF. If the input capture interrupt select bit (IIEGS) is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on interrupts are given in 3.3, Interrupts. To ensure proper input capture when the noise canceller is not used, the pulse width of the input capture signal should be at least 2o or 2oSUB. Upon reset, ICRGF is initialized to H'00. 3. Bit Initial value Read/Write Input capture register GR (ICRGR) 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 ICRGR is an 8-bit read-only register. When the rising edge of the input capture signal is detected, the TCG value at that time is sent to ICRGR. If the IIEGS bit is cleared to 0 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on interrupts are given in 3.3, Interrupts. To ensure proper input capture when the noise canceller is not used, the pulse width of the input capture signal should be at least 2o or 2oSUB. Upon reset, ICRGR is initialized to H'00. 227 4. Bit Timer mode register G (TMG) 7 OVFH 0 R/W * 6 OVFL 0 R/W * 5 OVIE 0 R/W 4 IIEGS 0 R/W 3 CCLR1 0 R/W 2 CCLR0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write Note: * Only 0 can be written, to clear flag. TMG is an 8-bit read/write register. It controls the choice of four input clocks, counter clear selection, and edge selection for input capture interrupt requests. It also indicates overflow status and enables or disables overflow interrupt requests. Upon reset, TMG is initialized to H'00. Bit 7: Timer overflow flag H (OVFH) Bit 7 is a status flag indicating that TCG overflowed (from H'FF to H'00) when the input capture signal was high. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 OVFH 0 1 Description Clearing conditions: After reading OVFH = 1, cleared by writing 0 to OVFH Setting conditions: Set when the value of TCG overflows from H'FF to H'00 (initial value) Bit 6: Timer overflow flag L (OVFL) Bit 6 is a status flag indicating that TCG overflowed (from H'FF to H'00) when the input capture signal was low, or in interval timer operation. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 OVFL 0 1 Description Clearing conditions: After reading OVFL = 1, cleared by writing 0 to OVFL Setting conditions: Set when the value of TCG overflows from H'FF to H'00 (initial value) 228 Bit 5: Timer overflow interrupt enable (OVIE) Bit 5 enables or disables TCG overflow interrupts. Bit 5 OVIE 0 1 Description TCG overflow interrupt disabled TCG overflow interrupt enabled (initial value) Bit 4: Input capture interrupt edge select (IIEGS) Bit 4 selects the input signal edge at which input capture interrupts are requested. Bit 4 IIEGS 0 1 Description Interrupts are requested at the rising edge of the input capture signal Interrupts are requested at the falling edge of the input capture signal (initial value) Bits 3, 2: Counter clear 1, 0 (CCLR1, CCLR0) Bits 3 and 2 designate whether TCG is cleared at the rising, falling, or both edges of the input capture signal, or is not cleared. Bit 3 CCLR1 0 0 1 1 Bit 2 CCLR0 0 1 0 1 Description TCG is not cleared TCG is cleared at the falling edge of the input capture signal TCG is cleared at the rising edge of the input capture signal TCG is cleared at both edges of the input capture signal (initial value) Bits 1, 0: Clock select (CKS1, CKS0) Bits 1 and 0 select the clock input to TCG from four internal clock signals. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description Internal clock: o/64 Internal clock: o/32 Internal clock: o/2 Internal clock: oW/2 (initial value) 229 9.6.3 Noise Canceller Circuit The noise canceller circuit built into the H8/3834U Series is a digital low-pass filter that rejects high-frequency pulse noise in the input at the input capture pin. The noise canceller circuit is enabled by the noise canceller select (NCS) bit in port mode register 2 (PMR2)*. Figure 9-6-2 shows a block diagram of the noise canceller circuit. Sampling clock Input capture signal C DQ latch C DQ latch C DQ latch C DQ latch C DQ latch Match detection circuit Noise canceller output t Sampling clock t: Selected by bits CKS1, CKS0. Figure 9-6-2 Block Diagram of Noise Canceller Circuit The noise canceller consists of five latch circuits connected in series, and a match detection circuit. When the noise canceller function is disabled (NCS = 0), the system clock is selected as the sampling clock. When the noise canceller is enabled (NCS = 1), the internal clock selected by bits CKS1 and CKS0 in TMG becomes the sampling clock. The input signal is sampled at the rising edge of this clock pulse. Data is considered correct when the outputs of all five latch circuits match. If they do not match, the previous value is retained. Upon reset, the noise canceller output is initialized after the falling edge of the input capture signal has been sampled five times. Accordingly, after the noise canceller function is enabled, pulses that have a pulse width five times greater than the sampling clock will be recognized as input capture signals. If the noise canceller circuit is not used, the input capture signal pulse width must be at least 2o or 2oSUB in order to ensure proper input capture operation. 230 Note: * Rewriting the NCS bit may cause an internal input capture signal to be generated. Figure 9-6-3 shows a typical timing diagram for the noise canceller circuit. In this example, a high-level input at the input capture pin is rejected as noise because its pulse width is less than five sampling clock o cycles. Input capture input signal Sampling clock Noise canceller output Rejected as noise Figure 9-6-3 Noise Canceller Circuit Timing (Example) 9.6.4 Timer Operation Timer G is an 8-bit timer with input capture and interval timer functions. 1. Timer G functions Timer G is an 8-bit timer/counter that functions as an input capture timer or an interval timer. These two functions are described below. * Input capture timer operation Timer G functions as an input capture timer when bit TMIG of port mode register 1 (PMR1) is set to 1.* At reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF (ICRGF), and input capture register GR (ICRGR) are all initialized to H'00. Immediately after reset, TCG begins counting an internal clock with a frequency of o divided by 64 (o/64). Three other internal clocks can be selected using bits CKS1 and CKS0 of TMG. At the rising edge/falling edge of the input capture signal input to pin TMIG, the value of TCG is copied into ICRGR/ICRGF. If the input edge is the same as the edge selected by the IIEGS bit of TMG, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, a CPU interrupt is requested. For details on interrupts, see section 3.3, Interrupts. 231 TCG can be cleared to 0 at the rising edge, falling edge, or both edges of the input capture signal as determined with bits CCLR1 and CCLR0 of TMG. If TCG overflows while the input capture signal is high, bit OVFH of TMG is set. If TCG overflows while the input capture signal is low, bit OVFL of TMG is set. When either of these bits is set, if bit OVIE of TMG is currently set to 1, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, then timer G requests a CPU interrupt. For further details see 3.3, Interrupts. Timer G has a noise canceller circuit that rejects high-frequency pulse noise in the input to pin TMIG. See 9.6.3, Noise Canceller Circuit, for details. Note: * Rewriting the TMIG bit may cause an internal input capture signal to be generated. * Interval timer operation Timer G functions as an interval timer when bit TMIG is cleared to 0 in PMR1. Following a reset, TCG starts counting cycles of the o/64 internal clock. This is one of four internal clock sources that can be selected by bits CKS1 and CKS0 of TMG. TCG counts up according to the selected clock source. When it overflows from H'FF to H'00, bit OVFL of TMG is set to 1. If bit OVIE of TMG is currently set to 1, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, then timer G requests a CPU interrupt. For further details see 3.3, Interrupts. 2. Count timing TCG is incremented by input pulses from an internal clock. TMG bits CKS1 and CKS0 select one of four internal clocks (o/64, o/32, o/2, oW/2) derived by dividing the system clock (o) or the watch clock (oW). 232 3. * Timing of internal input capture signals Timing with noise canceller function disabled Separate internal input capture signals are generated from the rising and falling edges of the external input signal. Figure 9-6-4 shows the timing of these signals. External input capture signal Internal input capture signal F Internal input capture signal R Figure 9-6-4 Input Capture Signal Timing (Noise Canceller Function Disabled) * Timing with noise canceller function enabled When input capture noise cancelling is enabled, the external input capture signal is routed via the noise canceller circuit, so the internal signals are delayed from the input edge by five sampling clock cycles. Figure 9-6-5 shows the timing. External input capture signal Sampling clock Noise canceller circuit output Internal input capture signal R Figure 9-6-5 Input Capture Signal Timing (Noise Canceller Function Enabled) 233 4. Timing of input capture Figure 9-6-6 shows the input capture timing in relation to the internal input capture signal. Internal input capture signal TCG N -1 N N +1 Input capture register H'XX N Figure 9-6-6 Input Capture Timing 5. TCG clear timing TCG can be cleared at the rising edge, falling edge, or both edges of the external input capture signal. Figure 9-6-7 shows the timing for clearing at both edges. External input capture signal Internal input capture signal F Internal input capture signal R TCG N H'00 N H'00 Figure 9-6-7 TCG Clear Timing 234 6. Timer G operation states Table 9-6-3 summarizes the timer G operation states. Table 9-6-3 Timer G Operation States Operation Mode TCG Input capture Interval ICRGF ICRGR TMG Reset Reset Reset Reset Reset Reset Active Sleep Watch Subactive Functions/ Halted* Subsleep Standby Functions* Functions* Halted Functions/ Halted Halted* Functions/ Halted Halted* Functions/ Retained Halted* Functions/ Retained Halted* Retained Retained Functions* Functions* Retained Functions/ Halted* Functions* Functions* Retained Functions/ Halted* Functions* Functions* Retained Functions/ Halted* Functions Retained Retained Functions Note: * In active mode and sleep mode, if oW/2 is selected as the TCG internal clock, since the system clock and internal clock are not synchronized with each other, a synchronization circuit is used. This may result in a count cycle error of up to 1/o (s). In subactive mode and subsleep mode, if oW/2 is selected as the TCG internal clock, regardless of the subclock o/SUB (oW/2, oW/4, oW/8) TCG and the noise canceller circuit run on an internal clock of oW/2. If any other internal clock is chosen, TCG and the noise canceller circuit will not run, and the input capture function will not operate. 9.6.5 Application Notes 1. Input clock switching and TCG operation Depending on when the input clock is switched, there will be cases in which TCG is incremented in the process. Table 9-6-4 shows the relation between internal clock switchover timing (selected in bits CKS1 and CKS0) and TCG operation. If an internal clock (derived from the system clock o or subclock oSUB) is used, an increment pulse is generated when a falling edge of the internal clock is detected. For this reason, in a case like No. 3 in table 9-6-4, where the clock is switched at a time such that the clock signal goes from high level before switching to low level after switching, the switchover is seen as a falling edge of the clock pulse, causing TCG to be incremented. 235 Table 9-6-4 Internal Clock Switching and TCG Operation Clock Level Before and After Modifying Bits CKS1 and CKS0 Goes from low level to low level No. 1 TCG Operation Clock before switching Clock after switching Count clock TCG N CKS bits modified N +1 2 Goes from low level to high level Clock before switching Clock after switching Count clock TCG N N +1 N +2 CKS bits modified 3 Goes from high level to low level Clock before switching Clock after switching * Count clock TCG N N +1 CKS bits modified N +2 4 Goes from high level to high level Clock before switching Clock after switching Count clock TCG N N +1 N +2 CKS bits modified Note: * The switchover is seen as a falling edge of the clock pulse, and TCG is incremented. 236 2. Note on rewriting port mode registers When a port mode register setting is modified to enable or disable the input capture function or input capture noise canceling function, note the following points. * Switching the function of the input capture pin When the function of the input capture pin is switched by modifying the TMIG bit in port mode register 1 (PMR1) an input capture edge may be recognized even though no valid signal edge has been input. This occurs under the conditions listed in table 9-6-5. Table 9-6-5 False Input Capture Edges Generating by Switching of Input Capture Pin Function Input Capture Edge Rising edge recognized Conditions TMIG pin level is high, and TMIG bit is changed from 0 to 1 TMIG pin level is high and NCS bit is changed from 0 to 1, then TMIG bit is changed from 0 to 1 before noise canceller circuit completes five samples TMIG pin level is high, and TMIG bit is changed from 1 to 0 TMIG pin level is low and NCS bit is changed from 0 to 1, then TMIG bit is changed from 0 to 1 before noise canceller circuit completes five samples TMIG pin level is high and NCS bit is changed from 0 to 1, then TMIG bit is changed from 1 to 0 before noise canceller circuit completes five samples Note: When pin P13 is not used for input capture, the input capture signal input to timer G is low. Falling edge recognized * Switching the input capture noise canceling function When modifying the NCS bit in port mode register 2 (PMR2) to enable or disable the input capture noise canceling function, first clear the TMIG bit to 0. Otherwise an input capture edge may be recognized even though no valid signal edge has been input. This occurs under the conditions listed in table 9-6-6. Table 9-6-6 False Input Capture Edges Generating by Switching of Noise Canceling Function Input Capture Edge Rising edge recognized Falling edge recognized Conditions TMIG bit is set to 1 and TMIG pin level changes from low to high, then NCS bit is changed from 1 to 0 before noise canceller circuit completes five samples TMIG bit is set to 1 and TMIG pin level changes from high to low, then NCS bit is changed from 1 to 0 before noise canceller circuit completes five samples 237 If switching of the pin function generates a false input capture edge matching the edge selected by the input capture interrupt edge select bit (IIEGS), the interrupt request flag will be set to 1, making it necessary to clear this flag to 0 before using the interrupt function. Figure 9-6-8 shows the procedure for modifying port mode register settings and clearing the interrupt request flag. The first step is to mask interrupts before modifying the port mode register. After modifying the port mode register setting, wait long enough for an input capture edge to be recognized (at least two system clocks when noise canceling is disabled; at least five sampling clocks when noise canceling is enabled), then clear the interrupt request flag to 0 (assuming it has been set to 1). An alternative procedure is to avoid having the interrupt request flag set when the pin function is switched, either by controlling the level of the input capture pin so that it does not satisfy the conditions in tables 9-6-5 and 9-6-6, or by setting the IIEGS bit of TMG to select the edge opposite to the falsely generated edge. Set I bit to 1 in CCR Disable interrupts (or disable by clearing interrupt enable bit in interrupt enable register 2) Modify port mode register Wait for TMIG to be recognized Clear interrupt request flag to 0 Modify port mode register setting, wait for input capture edge to be recognized (at least two system clocks when noise canceling is disabled; at least five sampling clocks when noise canceling is enabled), then clear interrupt request flag to 0 Clear I bit to 0 in CCR Enable interrupts Figure 9-6-8 Procedure for Modifying Port Mode Register and Clearing Interrupt Request Flag 238 9.6.6 Sample Timer G Application The absolute values of the high and low widths of the input capture signal can be measured by using timer G. The CCLR1 and CCLR0 bits of TMG should be set to 1. Figure 9-6-9 shows an example of this operation. Input capture signal H'FF Input capture register GF Input capture register GR H'00 TCG Counter cleared Figure 9-6-9 Sample Timer G Application 239 Section 10 Serial Communication Interface 10.1 Overview The H8/3834U Series is provided with a three-channel serial communication interface (SCI). Table 10-1-1 summarizes the functions and features of the three SCI channels. Table 10-1-1 Serial Communication Interface Functions Channel SCI1 Functions Synchronous serial transfer * Choice of 8-bit or 16-bit data length * Continuous clock output SCI2 Synchronous serial transfer Features * Choice of 8 internal clocks (o/1024 to o/2) or external clock * Open drain output possible * Interrupt requested at completion of transfer * Choice of 7 internal clocks (o/256 to o/2) or external clock * Automatic transfer of up to 32 bytes of data (send, receive, or simultaneous * Open drain output possible send/receive) * Interrupt requested at completion of * Chip select input * Strobe pulse output SCI3 Synchronous serial transfer * 8-bit data transfer * Send, receive, or simultaneous send/receive Asynchronous serial transfer * Built-in baud rate generator * Receive error detection * Break detection transfer or error * Interrupt requested at completion of transfer or error * Multiprocessor communication function * Choice of 7-bit or 8-bit data length * Choice of 1-bit or 2-bit stop bit length * Odd or even parity 241 10.2 SCI1 10.2.1 Overview Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit data. 1. * * Features Choice of 8-bit or 16-bit data length Choice of eight internal clock sources (o/1024, o/256, o/64, o/32, o/16, o/8, o/4, o/2) or an external clock Interrupt requested at completion of transfer * 242 2. Block diagram Figure 10-2-1 shows a block diagram of SCI1. o PSS SCK1 SCR1 Transfer bit counter SI1 SDRU SDRL SO1 IRRS1 Notation: SCR1: Serial control register 1 SCSR1: Serial control/status register 1 SDRU: Serial data register U SDRL: Serial data register L IRRS1: SCI1 interrupt request flag PSS: Prescaler S Figure 10-2-1 SCI1 Block Diagram 243 Internal data bus Transmit/receive control circuit SCSR1 3. Pin configuration Table 10-2-1 shows the SCI1 pin configuration. Table 10-2-1 Pin Configuration Name SCI1 clock pin SCI1 data input pin SCI1 data output pin Abbrev. SCK1 SI1 SO1 I/O I/O Input Output Function SCI1 clock input or output SCI1 receive data input SCI1 transmit data output 4. Register configuration Table 10-2-2 shows the SCI1 register configuration. Table 10-2-2 SCI1 Registers Name Serial control register 1 Serial control status register 1 Serial data register U Serial data register L Abbrev. SCR1 SCSR1 SDRU SDRL R/W R/W R/W R/W R/W Initial Value H'00 H'80 Not fixed Not fixed Address H'FFA0 H'FFA1 H'FFA2 H'FFA3 10.2.2 Register Descriptions 1. Bit Initial value Read/Write Serial control register 1 (SCR1) 7 SNC1 0 R/W 6 SNC0 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCR1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source, and the prescaler division ratio. Upon reset, SCR1 is initialized to H'00. Writing to this register during a transfer stops the transfer. 244 Bits 7 and 6: Operation mode select 1, 0 (SNC1, SNC0) Bits 7 and 6 select the operation mode. Bit 7 SNC1 0 0 1 1 Bit 6 SNC0 0 1 0 1 Description 8-bit synchronous transfer mode 16-bit synchronous transfer mode Continuous clock output mode*1 Reserved*2 (initial value) Notes: 1. Pins SI1 and SO1 should be used as general input or output ports. 2. Don't set bits SNC1 and SNC0 to 11. Bits 5 and 4: Reserved bits Bits 5 and 4 are reserved, but they can be written and read. Bit 3: Clock source select (CKS3) Bit 3 selects the clock source and sets pin SCK1 as an input or output pin. Bit 3 CKS3 0 1 Description Clock source is prescaler S, and pin SCK1 is output pin Clock source is external clock, and pin SCK1 is input pin (initial value) 245 Bits 2 to 0: Clock select (CKS2 to CKS 0) When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Serial Clock Cycle Prescaler Division o/1024 (initial value) o/256 o/64 o/32 o/16 o/8 o/4 o/2 o = 5 MHz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s -- o = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s 2. Bit Serial control/status register 1 (SCSR1) 7 -- 1 -- 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 R/W 0 STF 0 R/W Initial value Read/Write Note: * Only a write of 0 for flag clearing is possible. SCSR1 is an 8-bit read/write register indicating operation status and error status. Upon reset, SCSR1 is initialized to H'80. Bit 7: Reserved bit Bit 7 is reserved; it is always read as 1, and cannot be modified. 246 Bit 6: Extended data bit (SOL) Bit 6 sets the SO1 output level. When read, SOL returns the output level at the SO1 pin. After completion of a transmission, SO1 continues to output the value of the last bit of transmitted data. The SO1 output can be changed by writing to SOL before or after a transmission. The SOL bit setting remains valid only until the start of the next transmission. To control the level of the SO1 pin after transmission ends, it is necessary to write to the SOL bit at the end of each transmission. Do not write to this register while transmission is in progress, because that may cause a malfunction. Bit 6 SOL 0 Description Read Write 1 Read Write SO1 pin output level is low SO1 pin output level changes to low SO1 pin output level is high SO1 pin output level changes to high (initial value) Bit 5: Overrun error flag (ORER) When an external clock is used, bit 5 indicates the occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. Bit 5 ORER 0 1 Description Clearing conditions: After reading ORER = 1, cleared by writing 0 to ORER (initial value) Setting conditions: Set if a clock pulse is input after transfer is complete, when an external clock is used Bits 4 to 2: Reserved bits Bits 4 to 2 are reserved; they are always read as 0, and cannot be modified. Bit 1: Reserved bit Bit 1 is reserved; it should always be cleared to 0. 247 Bit 0: Start flag (STF) Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data. During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared to 0 upon completion of the transfer. It can therefore be used as a busy flag. Bit 0 STF 0 Description Read: Indicates that transfer is stopped Write: Invalid 1 Read: Indicates transfer in progress Write: Starts a transfer operation (initial value) 3. Bit Serial data register U (SDRU) 7 SDRU7 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 SDRU3 R/W 2 SDRU2 R/W 1 0 SDRU1 SDRU0 R/W R/W Initial value Read/Write Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed R/W SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit transfer (SDRL is used for the lower 8 bits). Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. SDRU must be written or read only after data transmission or reception is complete. If this register is written or read while a data transfer is in progress, the data contents are not guaranteed. The SDRU value upon reset is not fixed. 248 4. Bit Serial data register L (SDRL) 7 SDRL7 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 SDRL3 R/W 2 SDRL2 R/W 1 SDRL1 R/W 0 SDRL0 R/W Initial value Read/Write Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed R/W SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits). In 8-bit transfer, data written to SDRL is output from pin SO1 starting from the least significant bit (LSB). This data is than replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via SDRU. SDRL must be written or read only after data transmission or reception is complete. If this register is read or written while a data transfer is in progress, the data contents are not guaranteed. The SDRL value upon reset is not fixed. 10.2.3 Operation Data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external serial clock. Overrun errors can be detected when an external clock is used. 1. Clock The serial clock can be selected from a choice of eight internal clocks and an external clock. When an internal clock source is selected, pin SCK1 becomes the clock output pin. When continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock signal (o/1024 to o/2) selected in bits CKS2 to CKS0 is output continuously from pin SCK1. When an external clock is used, pin SCK1 is the clock input pin. 2. Data transfer format Figure 10-2-2 shows the data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the serial clock. 249 SCK 1 SO1 /SI 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 10-2-2 Transfer Format 3. * Data transfer operations Transmitting A transmit operation is carried out as follows. -- Set bit SO1 in port mode register 3 (PMR3) to 1, making pin P32/SO1 the SO1 output pin. Also set bit SCK1 in PMR3 to 1, making pin P30/SCK1 the SCK1 I/O pin. If necessary, set bit POF1 in port mode register 2 (PMR2) for NMOS open drain output at pin SO1. -- Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. -- Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL -- Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin SO1. -- After data transmission is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. 250 When an external clock is used, data is transmitted in synchronization with the serial clock input at pin SCK1. After data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. * Receiving A receive operation is carried out as follows. -- Set bit SI1 in port mode register 3 (PMR3) to 1, making pin P31/SI1 the SI1 input pin. Also set bit SCK1 in PMR3 to 1, making pin P30/SCK1 the SCK1 I/O pin. -- Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. -- Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI1. -- After data reception is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. -- Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL -- After data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the SCSR1 overrun error flag (bit ORER) is set to 1. 251 * Simultaneous transmit/receive A simultaneous transmit/receive operation is carried out as follows. -- Set bits SO1, SI1, and SCK1 in PMR3 to 1, making pin P32/SO1 the SO1 output pin, pin P31/SI1 the SI1 input pin, and pin P30/SCK1 the SCK1 I/O pin. If necessary, set bit POF1 in port mode register 2 (PMR2) for NMOS open drain output at pin SO1. -- Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. -- Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL -- Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO1. Receive data is input at pin SI1. -- After data transmission and reception are complete, bit IRRS1 in IRR1 is set to 1. -- Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin SCK1. After data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. 252 10.2.4 Interrupts SCI1 can generate an interrupt at the end of a data transfer. When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1 (IENR1). For further details, see 3.3, Interrupts. 10.2.5 Application Notes When an external clock is input at pin SCK1, bit STF in SCSR1 must first be set to 1 to start data transfer before inputting the external clock. 253 10.3 SCI2 10.3.1 Overview Serial communication interface 2 (SCI2) has a 32-bit data buffer for synchronous serial transfer of up to 32 bytes of data in one operation. 1. Features Features of SCI are listed below. * * Automatic transfer of up to 32 bytes of data Choice of seven internal clock sources (o/256, o/64, o/32, o/16, o/8, o/4, o/2) or an external clock Interrupts requested at completion of transfer or when an error occurs Gaps of 56, 24, or 8 internal clock cycles can be inserted between successive bytes of transferred data. Transfer can be started by chip select input. A strobe pulse can be output for each byte transferred. * * * * 254 2. Block diagram Figure 10-3-1 shows a block diagram of SCI2. PSS SCK 2 STAR STRB EDAR CS Transmit/receive control circuit SCR2 SCSR2 SO 2 Shift register Serial data buffer SI 2 Internal data bus IRRS2 Notation: STAR: EDAR: IRRS2: PSS: Start address register End address register SCI2 interrupt request flag (IRR2) Prescaler S Figure 10-3-1 SCI2 Block Diagram 255 3. Pin configuration Table 10-3-1 shows the SCI2 pin configuration. Table 10-3-1 Pin Configuration Name SCI2 clock pin SCI2 data input pin SCI2 data output pin SCI2 strobe pin SCI2 chip select pin Abbrev. SCK2 SI2 SO2 STRB CS I/O I/O Input Output Output Input Function SCI2 clock input/output SCI2 receive data input SCI2 transmit data output SCI2 strobe signal output SCI2 chip select input 4. Register configuration Table 10-3-2 shows the SCI2 register configuration. Table 10-3-2 SCI2 Registers Name Start address register End address register Serial control register 2 Serial control/status register 2 Serial data buffer (32 bytes) Abbrev. STAR EDAR SCR2 SCSR2 -- R/W R/W R/W R/W R/W R/W Initial Value H'E0 H'E0 H'E0 H'E0 Not fixed Address H'FFA4 H'FFA5 H'FFA6 H'FFA7 H'FF80 to H'FF9F 10.3.2 Register Descriptions 1. Bit Initial value Read/Write Start address register (STAR) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 STA4 0 R/W 3 STA3 0 R/W 2 STA2 0 R/W 1 STA1 0 R/W 0 STA0 0 R/W STAR is an 8-bit read/write register, for designating a transfer start address in the address space (H'FF80 to H'FF9F) allocated to the 32-byte data buffer. The lower 5 bits of STAR correspond to the lower 5 bits of the address. The extent of continuous data transfer is defined in STAR and in the end address register (EDAR). If the same value is designated by STAR and EDAR, only 1 byte of data is transferred. Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Upon reset, STAR is initialized to H'E0. 256 2. Bit End address register (EDAR) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 EDA4 0 R/W 3 EDA3 0 R/W 2 EDA2 0 R/W 1 EDA1 0 R/W 0 EDA0 0 R/W Initial value Read/Write EDAR is an 8-bit read/write register, for designating a transfer end address in the address space (H'FF80 to H'FF9F) allocated to the 32-byte data buffer. The lower 5 bits of EDAR correspond to the lower 5 bits of the address. The extent of continuous data transfer is defined in STAR and in EDAR. If the same value is designated by STAR and EDAR, only 1 byte of data is transferred. Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Upon reset, EDAR is initialized to H'E0. 3. Bit Initial value Read/Write Serial control register 2 (SCR2) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 GAP1 0 R/W 3 GAP0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCR2 is an 8-bit read/write register for selecting the serial clock, and for setting the gap inserted between data during continuous transfer when SCI2 uses an internal clock. Upon reset, SCR2 is initialized to H'E0. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. 257 Bits 4 and 3: Gap select (GAP1 to GAP0) When SCI2 uses an internal clock, gaps can be inserted between successive data bytes. Bits 4 and 3 designate the length of these gaps. During a gap, pin SCK2 remains at the high level. When no gap is inserted, the STRB signal stays at the low level. Bit 4 GAP1 0 0 1 1 Bit 3 GAP0 0 1 0 1 Description No gaps between bytes A gap of 8 clock cycles is inserted between bytes A gap of 24 clock cycles is inserted between bytes A gap of 56 clock cycles is inserted between bytes (initial value) Bits 2 to 0: Clock select (CKS2 to CKS0) Bits 2 to 0 select one of seven internal clock sources or an external clock. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Pin SCK2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SCK2 input Clock Source Serial Clock Cycle Prescaler Division o = 5 MHz o= 2.5 MHz o/256 (initial value) o/64 o/32 o/16 o/8 o/4 o/2 External clock -- 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s -- -- 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s -- SCK2 output Prescaler S 258 4. Bit Serial control/status register 2 (SCSR2) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 SOL 0 R/W 3 ORER 0 R/(W)* 2 WT 0 R/(W)* 1 ABT 0 R/(W)* 0 STF 0 R/W Initial value Read/Write Note: * Only a write of 0 for flag clearing is possible. SCSR2 is an 8-bit register indicating SCI2 operation status and error status. Upon reset, SCSR2 is initialized to H'E0. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: Extended data bit (SOL) Bit 4 sets the SO2 output level. When read, SOL returns the transmitted data output at the SO2 pin. After completion of a transmission, SO2 continues to output the value of the last bit of transmitted data. The SO2 output can be changed by writing to SOL before or after a transmission. The SOL bit setting remains valid only until the start of the next transmission. To control the level of the SO2 pin after transmission ends, it is necessary to write to the SOL bit at the end of each transmission. Note that if the STF bit is cleared to 0 to terminate a transmission in progress, the transmitted data will be modified when the bit is cleared. Bit 4 SOL 0 Description Read Write 1 Read Write SO2 pin output level is low SO2 pin output level changes to low SO2 pin output level is high SO2 pin output level changes to high (initial value) 259 Bit 3: Overrun error flag (ORER) When an external clock is used, bit 3 indicates the occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. Overrun errors are not detected while pin CS is at the high level. Bit 3 ORER 0 1 Description Clearing conditions: After reading ORER = 1, cleared by writing 0 to ORER (initial value) Setting conditions: Set if a clock pulse is input after transfer is complete, when an external clock is used Bit 2: Wait flag (WT) Bit 2 indicates that an attempt was made to read or write the 32-byte serial data buffer while a transfer was in progress, or while waiting for CS input. The read or write access is not carried out, and this bit is set to 1. Bit 2 WT 0 1 Description Clearing conditions: After reading WT = 1, cleared by writing 0 to WT (initial value) Setting conditions: An attempt was made to read or write the (32-byte) serial data buffer during a transfer operation or while waiting for CS input 260 Bit 1: Abort flag (ABT) Bit 1 indicates that CS went to high during data transfer. When the CS input function is selected, if a high-level signal is detected at pin CS during a transfer, the transfer is immediately aborted and this bit is set to 1. At the same time bit IRRS2 in interrupt request register 2 (IRR2) is set to 1, and pins SCK2 and SO2 go to the high-impedance state. Data in the (32-byte) serial data buffer and values in the internal registers other than SCSR2 remain unchanged. Transfer cannot take place while this bit is set to 1. It must be cleared to 0 before resuming the transfer. Bit 1 ABT 0 1 Description Clearing conditions: After reading ABT = 1, cleared by writing 0 to ABT Setting conditions: When pin CS goes high during a transfer (initial value) Bit 0: Start/busy flag (STF) Bit 0 controls the start of a transfer. If bit CS = 0 in PMR2, setting bit STF to 1 causes SCI2 to start transferring data. If bit CS = 1 in PMR2, then after STF is set to 1, SCI2 starts transferring data when CS goes low. This bit stays at 1 during the transfer or while waiting for CS input; it is cleared to 0 after the transfer is completed or when the transfer is aborted by CS. It can therefore be used as a busy flag. Clearing this bit to 0 during a transfer aborts the transfer. The contents of the (32-byte) serial data buffer and of internal registers other than SCSR2 remain unchanged. Bit 0 STF 0 Explanation Read: Indicates that transfer is stopped Write: Stops a transfer operation 1 Read: Indicates transfer in progress or waiting for CS input Write: Starts a transfer operation (initial value) 261 10.3.3 Operation SCI2 has a 32-byte serial data buffer, making possible continuous transfer of up to 32 bytes of data with one operation. SCI2 transmits and receives data in synchronization with clock pulses. Depending on register settings, it can transmit, receive, or transmit and receive simultaneously. When it transmits but does not receive, the serial data buffer values are retained after the transmission is completed. Either an internal clock or external clock may be selected as the serial clock. When an internal clock is selected, gaps may be inserted between the data bytes. It is also possible to output a strobe signal at pin STRB. When an external clock is selected, the overrun flag allows detection of erroneous operation due to unwanted clock input. Transfers can be started or aborted by input at pin CS. Abort is indicated by means of an abort flag. 1. Clock The serial clock can be selected from a choice of six internal clock sources or an external clock. When an internal clock source is selected, pin SCK2 becomes the clock output pin. 2. Data transfer format Figure 10-3-2 and figure 10-3-3 show the SCI2 data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the serial clock. When SCI2 operates on an internal clock, a gap can be inserted between each byte of transferred data and the next, as shown in figure 10-3-3. During this gap, pin SCK2 outputs a high-level signal. Also, a strobe pulse can be output at pin STRB. The length of the gap is designated in bits GAP1 and GAP0 in serial control register 2 (SCR2). 262 SCK 2 SO 2 /SI 2 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Figure 10-3-2 Data Transfer Format (No Gaps between Data) 263 CS STRB Transfer completed Transfer started 8, 24, or 56 clock cycles SCK2 SO2 /SI 2 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Figure 10-3-3 Data Transfer Format (Gap Inserted between Data) 264 CS STRB Transfer completed Transfer started 3. * Data transfer operations SCI2 initialization Data transfer on SCI2 first of all requires that SCI2 be initialized by software as follows. -- With bit STF cleared to 0 in SCSR2, select pin functions and the transfer mode in registers PMR2, PMR3, STAR, EDAR, and SCR2. -- The SCI2 pins double as general input/output ports. Switching between port and SCI2 functions is controlled in PMR3. CMOS output or NMOS open drain output can be selected in PMR2. The serial clock and gaps between transferred bytes are set in SCR2. -- The start and end addresses of the transfer data area are set in STAR and EDAR. If the end address is set smaller than the start address, as shown in figure 10-3-4, the transfer wraps around from H'FF9F to H'FF80 and continues to the end address. If the start address and end address are the same, only one byte of data will be transferred. H'FF80 End End address Start Start address H'FF9F Figure 10-3-4 Operation When End Address is Smaller than Start Address 265 * Transmitting A transmit operation is carried out as follows. -- Set bit SO2 in port mode register 3 (PMR3) to 1, making pin P35/SO2 the SO2 output pin. Also set bit SCK2 in PMR3 to 1, making pin P33/SCK2 the SCK2 I/O pin. If necessary, set bit POF2 in port mode register 2 (PMR2) for NMOS open-drain output at pin SO2, and set bits CS and STRB in PMR3 to designate use of the CS and STRB pin functions. -- Select the serial clock and, in the case of internal clock operation, the data gap in SCR2. -- Write transmit data in the serial data buffer. This data will remain in the data buffer after completion of the transfer. It is not necessary to rewrite the buffer when the same data is retransmitted. -- Set the start address in the lower 5 bits of STAR, and the end address in the lower 5 bits of EDAR. -- Set the start/busy flag (STF) to 1. If bit CS = 0 in PMR3, transmission starts as soon as STF is set to 1. If CS = 1 in PMR3, transmission starts when CS goes low. -- After data transmission is complete, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1, and bit STF is cleared to 0. When an internal clock is used, a serial clock is output from pin SCK2 in synchronization with the transmit data. After data transmission is completed, the serial clock is not output until bit STF is set again. During this time, pin SO2 continues to output the value of the last bit transmitted. 266 When an external clock is used, data is transmitted in synchronization with the serial clock input at pin SCK2. After data transmission is completed, an overrun occurs if the serial clock continues to be input; no data is transmitted and the SCSR2 overrun error flag (bit ORER) is set to 1. Pin SO2 continues to output the value of the last preceding bit. Overrun errors are not detected when both pin CS is at the high level and PMR3 bit CS = 1. While transmission is stopped, the output value of pin SO2 can be changed by rewriting bit SOL in SCSR2. During a transmission or while waiting for CS input, the CPU cannot read or write the data buffer. If a read instruction is executed, H'FF will be read; if a write instruction is executed, the buffer contents will not change. In either case the wait flag (bit WT) in SCSR2 will be set to 1. If bit CS = 1 in PMR3 and during transmission a high-level signal is detected at pin CS, the transmit operation will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same time bit IRRS2 in interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared to 0. Pins SCK2 and SO2 will go to the high-impedance state. Data transfer is not possible while bit ABT is set to 1. It must be cleared before resuming the transfer. * Receiving A receive operation is carried out as follows. -- Set bits SI2 and SCK2 in port mode register 3 (PMR3) to 1, designating use of the SI2 and SCK2 pin functions. If necessary, set bit CS in PMR3 to select the CS pin function. -- Select the serial clock and, in the case of internal clock operation, the data gap in SCR2. -- Allocate an area to hold the received data in the serial data buffer by designating the receive start address in the lower 5 bits of the start address register (STAR) and the receive end address in the lower 5 bits of the end address register (EDAR). -- Set the start/busy flag (bit STF) to 1. If bit CS = 0 in PMR3, receiving starts as soon as STF is set. If CS = 1 in PMR3, receiving starts when CS goes low. -- After receiving is completed, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1, and bit STF is cleared to 0. -- Read the received data from the serial data buffer. 267 If an internal clock is used, a serial clock is output from pin SCK2 when the receive operation starts. After receiving is completed, the serial clock is not output until bit STF is set again. When an external clock source is used, data is received in synchronization with the clock input at pin SCK2. After receiving is completed, an overrun occurs if the serial clock continues to be input; no further data is received and the SCSR2 overrun error flag (bit ORER) is set to 1. Overrun errors are not detected when both pin CS is high and bit CS = 1 in PMR3. While receiving or while waiting for CS input, the CPU cannot read or write the data buffer. If a read instruction is executed, H'FF will be read; if a write instruction is executed the buffer contents will not change. In either case the wait flag (bit WT) in SCSR2 will be set to 1. If bit CS = 1 in PMR3 and a high-level signal is detected at pin CS during receiving, the receive operation will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same time bit IRRS2 in interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared to 0. Pins SCK2 and SO2 will go to the high-impedance state. Data transfer is not possible while bit ABT is set to 1. It must be cleared before resuming the transfer. * Simultaneous transmit/receive A simultaneous transmit/receive operation is carried out as follows. -- Set bits SO2, SI2, and SCK2 in PMR3 to 1, designating use of the SO2, SI2, and SCK2 pin functions. If necessary, set bit POF2 in port mode register 2 (PMR2) for NMOS open-drain output at pin SO2, and set bits CS and STRB to designate use of the CS and STRB pin functions. -- Select the transfer clock and, in the case of internal clock operation, the data gap in SCR2. -- Write transmit data in the serial data buffer. In simultaneous transmit/receive, received data replaces transmitted data at the same buffer addresses. -- Set the transfer start address in the lower 5 bits of STAR, and the transfer end address in the lower 5 bits of EDAR. -- Set the start/busy flag (bit STF) to 1. If bit CS = 0 in PMR3, the transmit/receive transfer starts as soon as STF is set to 1. If CS = 1 in PMR3, transfer operations start when CS goes low. 268 -- After data transfer is completed, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1, and bit STF is cleared to 0. -- Read the received data from the serial data buffer. If an internal clock is used, a serial clock is output from pin SCK2 when the transfer begins. After the transfer is completed, the serial clock is not output until bit STF is set again. During this time, pin SO2 continues to output the value of the last bit transmitted. When an external clock is used, data is transferred in synchronization with the serial clock input at pin SCK2. After the transfer is completed, an overrun occurs if the serial clock continues to be input; no transfer operation takes place and the SCSR2 overrun error flag (bit ORER) is set to 1. Pin SO2 continues to output the value of the last transmitted bit. Overrun errors are not detected when both pin CS is high and bit CS = 1 in PMR3. While data transfer is stopped, the output value of pin SO2 can be changed by rewriting bit SOL in SCSR2. During a transfer or while waiting for CS input, the CPU cannot read or write the data buffer. If a read instruction is executed, H'FF will be read; if a write instruction is executed the buffer contents will not change. In either case the wait flag (bit WT) in SCSR2 will be set to 1. If bit CS = 1 in PMR3 and during the transfer a high-level signal is detected at pin CS, the transfer will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same time bit IRRS2 in interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared to 0. Pins SCK2 and SO2 will go to the high-impedance state. Data transfer is not possible while bit ABT is set to 1. It must be cleared before resuming the transfer. 10.3.4 Interrupts SCI2 can generate interrupts when a transfer is completed or when a transfer is aborted by CS. These interrupts have the same vector address. When the above conditions occur, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1. SCI2 interrupt requests can be enabled or disabled in bit IENS2 of interrupt enable register 2 (IENR2). For further details, see 3.3, Interrupts. When a transfer is aborted by CS, an overrun error occurs, or a read or write of the serial data buffer is attempted during a transfer or while waiting for CS input, the ABT, ORER, or WT bit in SCSR2 is set to 1. These bits can be used to determine the cause of the error. 10.3.5 Application Notes When an external clock is input at pin SCK2, bit STF in SCSR2 must first be set to 1 to start data transfer before inputting the external clock. 269 10.4 SCI3 10.4.1 Overview Serial communication interface 3 (SCI3) has both synchronous and asynchronous serial data communication capabilities. It also has a multiprocessor communication function for serial data communication among two or more processors. 1. Features SCI3 features are listed below. * a. Selection of asynchronous or synchronous mode Asynchronous mode SCI3 can communicate with a UART (universal asynchronous receiver/transmitter), ACIA (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. -- -- -- -- -- -- b. Data length: seven or eight bits Stop bit length: one or two bits Parity: even, odd, or none Multiprocessor bit: one or none Receive error detection: parity, overrun, and framing errors Break detection: by reading the RXD level directly when a framing error occurs Synchronous mode Serial data communication is synchronized with a clock signal. SCI3 can communicate with other chips having a clocked synchronous communication function. -- Data length: eight bits -- Receive error detection: overrun errors * Full duplex communication The transmitting and receiving sections are independent, so SCI3 can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. 270 * * * Built-in baud rate generator with selectable bit rates. Internal or external clock may be selected as the transfer clock source. There are six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error. Block diagram 2. Figure 10-4-1 shows a block diagram of SCI3. SCK 3 External clock Baud rate generator BRC Clock Internal clock (o/64, o/16, o/4, o) BRR SMR Transmit/receive control SCR3 SSR Internal data bus Interrupt requests (TEI, TXI, RXI, ERI) TXD TSR TDR RXD RSR RDR Notation: RSR: RDR: TSR: TDR: SMR: SCR3: SSR: BRR: BRC: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Figure 10-4-1 SCI3 Block Diagram 271 3. Pin configuration Table 10-4-1 shows the SCI3 pin configuration. Table 10-4-1 Pin Configuration Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbrev. SCK3 RXD TXD I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output 4. Register configuration Table 10-4-2 shows the SCI3 internal register configuration. Table 10-4-2 SCI3 Registers Name Serial mode register Bit rate register Serial control register 3 Transmit data register Serial status register Receive data register Transmit shift register Receive shift register Bit rate counter Abbrev. SMR BRR SCR3 TDR SSR RDR TSR RSR BRC R/W R/W R/W R/W R/W R/W R -- -- -- Initial Value H'00 H'FF H'00 H'FF H'84 H'00 -- -- -- Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD -- -- -- 272 10.4.2 Register Descriptions 1. Bit Read/Write Receive shift register (RSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- The receive shift register (RSR) is for receiving serial data. Serial data is input in LSB-first order into RSR from pin RXD, converting it to parallel data. After each byte of data has been received, the byte is automatically transferred to the receive data register (RDR). RSR cannot be read or written directly by the CPU. 2. Bit Initial value Read/Write Receive data register (RDR) 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 2 RDR2 0 R 1 RDR1 0 R 0 RDR0 0 R The receive data register (RDR) is an 8-bit register for storing received serial data. Each time a byte of data is received, the received data is transferred from the receive shift register (RSR) to RDR, completing a receive operation. Thereafter RSR again becomes ready to receive new data. RSR and RDR form a double buffer mechanism that allows data to be received continuously. RDR is exclusively for receiving data and cannot be written by the CPU. RDR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. 273 3. Bit Transmit shift register (TSR) 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- Read/Write The transmit shift register (TSR) is for transmitting serial data. Transmit data is first transferred from the transmit data register (TDR) to TSR, then is transmitted from pin TXD, starting from the LSB (bit 0). After one byte of data has been sent, the next byte is automatically transferred from TDR to TSR, and the next transmission begins. If no data has been written to TDR (1 is set in TDRE), there is no data transfer from TDR to TSR. TSR cannot be read or written directly by the CPU. 4. Bit Initial value Read/Write Transmit data register (TDR) 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W 2 TDR2 1 R/W 1 TDR1 1 R/W 0 TDR0 1 R/W The transmit data register (TDR) is an 8-bit register for holding transmit data. When SCI3 detects that the transmit shift register (TSR) is empty, it shifts transmit data written in TDR to TSR and starts serial data transmission. While TSR is transmitting serial data, the next byte to be transmitted can be written to TDR, realizing continuous transmission. TDR can be read or written by the CPU at all times. TDR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. 274 5. Bit Serial mode register (SMR) 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write The serial mode register (SMR) is an 8-bit register for setting the serial data communication format and for selecting the clock source of the baud rate generator. SMR can be read and written by the CPU at any time. SMR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7: Communication mode (COM) Bit 7 selects asynchronous mode or synchronous mode as the serial data communication mode. Bit 7 COM 0 1 Description Asynchronous mode Synchronous mode (initial value) Bit 6: Character length (CHR) Bit 6 selects either 7 bits or 8 bits as the data length in asynchronous mode. In synchronous mode the data length is always 8 bits regardless of the setting here. Bit 6 CHR 0 1 Description 8-bit data 7-bit data* (initial value) Note: * When 7-bit data is selected as the character length in asynchronous mode, the MSB (bit 7) in the transmit data register is not transmitted. 275 Bit 5: Parity enable (PE) In asynchronous mode, bit 5 selects whether or not a parity bit is to be added to transmitted data and checked in received data. In synchronous mode there is no adding or checking of parity regardless of the setting here. Bit 5 PE 0 1 Description Parity bit adding and checking disabled Parity bit adding and checking enabled* (initial value) Note: * When PE is set to 1, then either odd or even parity is added to transmit data, depending on the setting of the parity mode bit (PM). When data is received, it is checked for odd or even parity as designated in bit PM. Bit 4: Parity mode (PM) In asynchronous mode, bit 4 selects whether odd or even parity is to be added to transmitted data and checked in received data. The setting here is valid only if parity adding/checking is enabled in bit PE. In synchronous mode, or if parity adding/checking is disabled in bit PE, bit PM is ignored. Bit 4 PM 0 1 Description Even parity*1 Odd parity*2 (initial value) Notes: 1. When even parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an even number. When data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an even number. 2. When odd parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an odd number. When data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an odd number. 276 Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. This setting is valid only in asynchronous mode. In synchronous mode a stop bit is not added, so this bit is ignored. Bit 3 STOP 0 1 Description 1 stop bit*1 2 stop bits*2 (initial value) Notes: 1. When data is transmitted, one 1 bit is added at the end of each transmitted character as the stop bit. 2. When data is transmitted, two 1 bits are added at the end of each transmitted character as the stop bits. When data is received, only the first stop bit is checked regardless of the stop bit length. If the second stop bit value is 1 it is treated as a stop bit; if it is 0, it is treated as the start bit of the next character. Bit 2: Multiprocessor mode (MP) Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor communication function is enabled, the parity enable (PE) and parity mode (PM) settings are ignored. The MP bit is valid only in asynchronous mode; it should be cleared to 0 in synchronous mode. See 10.4.6, for details on the multiprocessor communication function. Bit 2 MP 0 1 Description Multiprocessor communication function disabled Multiprocessor communication function enabled (initial value) 277 Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0) Bits 1 and 0 select the clock source for the built-in baud rate generator. A choice of o/64, o/16, o/4, or o is made in these bits. See 8, Bit rate register, below for information on the clock source and bit rate register settings, and their relation to the baud rate. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description o clock o/4 clock o/16 clock o/64 clock (initial value) 6. Bit Serial control register 3 (SCR3) 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value Read/Write Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive operations, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the serial clock source. SCR3 can be read and written by the CPU at any time. SCR3 is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. 278 Bit 7: Transmit interrupt enable (TIE) Bit 7 enables or disables the transmit data empty interrupt (TXI) request when data is transferred from TDR to TSR and the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1. The TXI interrupt can be cleared by clearing bit TDRE to 0, or by clearing bit TIE to 0. Bit 7 TIE 0 1 Description Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled (initial value) Bit 6: Receive interrupt enable (RIE) Bit 6 enables or disables the receive error interrupt (ERI), and the receive data full interrupt (RXI) requested when data is transferred from RSR to RDR and the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1. RXI and ERI interrupts can be cleared by clearing SSR flag RDRF, or flags FER, PER, and OER to 0, or by clearing bit RIE to 0. Bit 6 RIE 0 1 Description Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled (initial value) Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Bit 5: Transmit enable (TE) Bit 5 enables or disables the start of a transmit operation. Bit 5 TE 0 1 Description Transmit operation disabled*1 (TXD is a general I/O port) Transmit operation enabled*2 (TXD is the transmit data pin) (initial value) Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is fixed at 1. 2. In this state, writing transmit data in TDR clears bit TDRE in SSR to 0 and starts serial data transmission. Before setting TE to 1 it is necessary to set the transmit format in SMR. 279 Bit 4: Receive enable (RE) Bit 4 enables or disables the start of a receive operation. Bit 4 RE 0 1 Description Receive operation disabled*1 (RXD is a general I/O port) Receive operation enabled*2 (RXD is the receive data pin) (initial value) Notes: 1. When RE is cleared to 0, this has no effect on the SSR flags RDRF, FER, PER, and OER, which retain their states. 2. Serial data receiving begins when, in this state, a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Before setting RE to 1 it is necessary to set the receive format in SMR. Bit 3: Multiprocessor interrupt enable (MPIE) Bit 3 enables or disables multiprocessor interrupt requests. This setting is valid only in asynchronous mode, and only when the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1. It applies only to data receiving. This bit is ignored when COM is set to 1 or when bit MP is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupt request disabled (ordinary receive operation) Clearing condition: Multiprocessor bit receives a data value of 1 1 Multiprocessor interrupt request enabled* (initial value) Note: * SCI3 does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set status flags RDRF, FER, and OER in SSR. Until a multiprocessor bit value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are disabled and serial status register (SSR) flags RDRF, FER, and OER are not set. When the multiprocessor bit receives a 1, the MPBR bit of SSR is set to 1, MPIE is automatically cleared to 0, RXI and ERI interrupts are enabled (provided bits TIE and RIE in SCR3 are set to 1), and setting of the RDRF, FER, and OER flags is enabled. 280 Bit 2: Transmit end interrupt enable (TEIE) Bit 2 enables or disables the transmit end interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted. Bit 2 TEIE 0 1 Description Transmit end interrupt (TEI) disabled Transmit end interrupt (TEI) enabled* (initial value) Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit end bit (TEND) to 0, or by clearing bit TEIE to 0. Bits 1 and 0: Clock enable 1, 0 (CKE1, CKE0) Bits 1 and 0 select the clock source and enable or disable clock output at pin SCK3. The combination of bits CKE1 and CKE0 determines whether pin SCK3 is a general I/O port, a clock output pin, or a clock input pin. Note that the CKE0 setting is valid only when operation is in asynchronous mode using an internal clock. This bit is invalid in synchronous mode or when using an external clock (CKE1 = 1). In synchronous mode and in external clock mode, clear CKE0 to 0. After setting bits CKE1 and CKE0, the operation mode must first be set in the serial mode register (SMR). See table 10-4-9 in 10.4.3, Operation, for details on clock source selection. Bit 1 CKE1 0 Bit 0 CKE0 0 Communication Mode Asynchronous Synchronous 0 1 Asynchronous Synchronous 1 0 Asynchronous Synchronous 1 1 Asynchronous Synchronous Clock Source Internal clock Internal clock Internal clock Reserved External clock External clock Reserved Reserved SCK3 Pin Function I/O port*1 Serial clock output*1 Clock output*2 Reserved Clock input*3 Serial clock input Reserved Reserved Notes: 1. Initial value 2. A clock is output with the same frequency as the bit rate. 3. Input a clock with a frequency 16 times the bit rate. 281 7. Bit Serial status register (SSR) 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 OER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPBR 0 R 0 MPBT 0 R/W Initial value Read/Write Note: * Only 0 can be written for flag clearing. The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3 states, and containing the multiprocessor bits. SSR can be read and written by the CPU at any time, but the CPU cannot write a 1 to the status flags TDRE, RDRF, OER, PER, and FER. To clear these flags to 0 it is first necessary to read a 1. Bit 2 (TEND) and bit 1 (MPBR) are read-only bits and cannot be modified. SSR is initialized to H'84 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7: Transmit data register empty (TDRE) Bit 7 is a status flag indicating that data has been transferred from TDR to TSR. Bit 7 TDRE 0 Description Indicates that transmit data written to TDR has not been transferred to TSR Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE. When data is written to TDR by an instruction. 1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR Setting conditions: When bit TE in SCR3 is cleared to 0. When data is transferred from TDR to TSR. (initial value) 282 Bit 6: Receive data register full (RDRF) Bit 6 is a status flag indicating whether there is receive data in RDR. Bit 6 RDRF 0 Description Indicates there is no receive data in RDR Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF. When data is read from RDR by an instruction. 1 Indicates that there is receive data in RDR Setting condition: When receiving ends normally, with receive data transferred from RSR to RDR Note: If a receive error is detected at the end of receiving, or if bit RE in serial control register 3 (SCR3) is cleared to 0, RDR and RDRF are unaffected and keep their previous states. An overrun error (OER) occurs if receiving of data is completed while bit RDRF remains set to 1. If this happens, receive data will be lost. (initial value) Bit 5: Overrun error (OER) Bit 5 is a status flag indicating that an overrun error has occurred during data receiving. Bit 5 OER 0 Description Indicates that data receiving is in progress or has been completed*1 Clearing condition: After reading OER = 1, cleared by writing 0 to OER 1 Indicates that an overrun error occurred in data receiving*2 Setting condition: When data receiving is completed while RDRF is set to 1 Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, OER is unaffected and keeps its previous state. 2. RDR keeps the data received prior to the overrun; data received after that is lost. While OER is set to 1, data receiving cannot be continued. In synchronous mode, data transmitting cannot be continued either. (initial value) 283 Bit 4: Framing error (FER) Bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. Bit 4 FER 0 Description Indicates that data receiving is in progress or has been completed*1 Clearing condition: After reading FER = 1, cleared by writing 0 to FER 1 Indicates that a framing error occurred in data receiving Setting condition: The stop bit at the end of receive data is checked and found to be 0*2 Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, FER is unaffected and keeps its previous state. 2. When two stop bits are used only the first stop bit is checked, not the second. When a framing error occurs, receive data is transferred to RDR but RDRF is not set. While FER is set to 1, data receiving cannot be continued. In synchronous mode, data transmitting cannot be continued either. (initial value) Bit 3: Parity error (PER) Bit 3 is a status flag indicating that a parity error has occurred during asynchronous receiving. Bit 3 PER 0 Description Indicates that data receiving is in progress or has been completed*1 Clearing condition: After reading PER = 1, cleared by writing 0 to PER 1 Indicates that a parity error occurred in data receiving*2 Setting condition: When the sum of 1s in received data plus the parity bit does not match the parity mode bit (PM) setting in the serial mode register (SMR) Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, PER is unaffected and keeps its previous state. 2. When a parity error occurs, receive data is transferred to RDR but RDRF is not set. While PER is set to 1, data receiving cannot be continued. In synchronous mode, data transmitting cannot be continued either. (initial value) 284 Bit 2: Transmit end (TEND) Bit 2 is a status flag indicating that TDRE was set to 1 when the last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified directly. Bit 2 TEND 0 Description Indicates that transmission is in progress Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE. When data is written to TDR by an instruction. 1 Indicates that a transmission has ended Setting conditions: When bit TE in SCR3 is cleared to 0. If TDRE is set to 1 when the last bit of a transmitted character is sent. (initial value) Bit 1: Multiprocessor bit receive (MPBR) Bit 1 holds the multiprocessor bit in data received in asynchronous mode using a multiprocessor format. MPBR is a read-only bit and cannot be modified. Bit 1 MPBR 0 1 Description Indicates reception of data in which the multiprocessor bit is 0* Indicates reception of data in which the multiprocessor bit is 1 (initial value) Note: * If bit RE is cleared to 0 while a multiprocessor format is in use, MPBR retains its previous state. 285 Bit 0: Multiprocessor bit transmit (MPBT) Bit 0 holds the multiprocessor bit to be added to transmitted data when a multiprocessor format is used in asynchronous mode. Bit MPBT is ignored when synchronous mode is chosen, when the multiprocessor communication function is disabled, or when data transmission is disabled. Bit 0 MPBT 0 1 Description The multiprocessor bit in transmit data is 0 The multiprocessor bit in transmit data is 1 (initial value) 8. Bit Bit rate register (BRR) 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W 2 BRR2 1 R/W 1 BRR1 1 R/W 0 BRR0 1 R/W Initial value Read/Write The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit rate. BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Table 10-4-3 gives examples of how BRR is set in asynchronous mode. The values in table 10-4-3 are for active (high-speed) mode. 286 Table 10-4-3 BRR Settings and Bit Rates in Asynchronous Mode (1) OSC (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 0 0 0 0 0 -- -- -- 0 -- N 70 207 103 51 25 12 -- -- -- 0 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- -- 0 -- n 1 0 0 0 0 0 0 0 0 -- 0 2.4576 N 86 255 127 63 31 15 7 3 1 -- 0 Error (%) +0.31 0 0 0 0 0 0 0 0 -- 0 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- 4 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- 0 -- n 1 1 0 0 0 0 0 0 -- -- -- 4.194304 N 148 108 217 108 54 26 13 6 -- -- -- Error (%) -0.04 +0.21 +0.21 +0.21 -0.70 +1.14 -2.48 -2.48 -- -- -- Table 10-4-3 BRR Settings and Bit Rates in Asynchronous Mode (2) OSC (MHz) 4.9152 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 -- 0 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0 0 0 0 0 0 0 0 -- 0 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 6 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 -2.34 0 -- n 2 1 1 0 0 0 0 0 0 -- 0 7.3728 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) +0.70 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 8 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- 0 -- 287 Table 10-4-3 BRR Settings and Bit Rates in Asynchronous Mode (3) OSC (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) +0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 10 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 +1.73 0 +1.73 Notes: 1. Settings should be made so that error is within 1%. 2. BRR setting values are derived by the following equation. N= OSC 64 x 22n x B x 106 - 1 B: N: OSC: n: Bit rate (bits/s) BRR baud rate generator setting (0 N 255) Value of oOSC (MHz) Baud rate generator input clock number (n = 0, 1, 2, 3) 3. The error values in table 10-4-3 were derived by performing the following calculation and rounding off to two decimal places. Error (%) = B-R R x 100 B: Bit rate found from n, N, and OSC R: Bit rate listed in left column of table 10-4-3 288 The meaning of n is shown in table 10-4-4. Table 10-4-4 Relation between n and Clock SMR Setting n 0 1 2 3 Clock o o/4 o/16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Table 10-4-5 shows the maximum bit rate for selected frequencies in asynchronous mode. Values in table 10-4-5 are for active (high-speed) mode. Table 10-4-5 Maximum Bit Rate at Selected Frequencies (Asynchronous Mode) Setting OSC (MHz) 2 2.4576 4 4.194304 4.9152 6 7.3728 8 9.8304 10 Maximum Bit Rate (bits/s) 31250 38400 62500 65536 76800 93750 115200 125000 153600 156250 n 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 289 Table 10-4-6 shows typical BRR settings in synchronous mode. Values in table 10-4-6 are for active (high-speed) mode. Table 10-4-6 Typical BRR Settings and Bit Rates (Synchronous Mode) OSC (MHz) Bit Rate (bits/s) 110 250 500 1K 2.5K 5K 10K 25K 50K 100K 250K 500K 1M 2.5M Notes: Blank: Cannot be set --: Can be set, but error will result *: Continuous transfer not possible at this setting BRR setting values are derived by the following equation. N= B: N: OSC: n: OSC 8 x 22n x B x 106 - 1 2 n -- 1 1 0 0 0 0 0 0 -- 0 N -- 249 124 249 99 49 24 9 4 -- 0* n -- 2 1 1 0 0 0 0 0 0 0 0 4 N -- 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- -- -- -- 1 0 0 0 0 -- 0 -- -- 10 N -- -- -- -- 124 249 124 49 24 -- 4 -- -- Bit rate (bits/s) BRR baud rate generator setting (0 N 255) Value of oOSC (MHz) Baud rate generator input clock number (n = 0, 1, 2, 3) 290 The meaning of n is shown in table 10-4-7. Table 10-4-7 Relation between n and Clock SMR Setting n 0 1 2 3 Clock o o/4 o/16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 10.4.3 Operation SCI3 supports serial data communication in both asynchronous mode, where each character transferred is synchronized separately, and synchronous mode, where transfer is synchronized by clock pulses. The choice of asynchronous mode or synchronous mode, and the communication format, is made in the serial mode register (SMR), as shown in table 10-4-8. The SCI3 clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3), as shown in table 10-4-9. 1. Asynchronous mode -- Data length: choice of 7 bits or 8 bits -- Transmit/receive format options include addition of parity bit, multiprocessor bit, and one or two stop bits (character length depends on this combination of options). -- Framing error (FER), parity error (PER), overrun error (OER), and line breaks can be detected when data is received. -- Clock source: Choice of internal clocks or an external clock When an internal clock is selected: Operates on baud rate generator clock. A clock can be output with the same frequency as the bit rate. When an external clock is selected: A clock input with a frequency 16 times the bit rate is required (internal baud rate generator is not used). 291 2. Synchronous mode -- Transfer format: 8 bits -- Overrun error can be detected when data is received. -- Clock source: Choice of internal clocks or an external clock When an internal clock is selected: Operates on baud rate generator clock, and outputs a serial clock. When an external clock is selected: The internal baud rate generator is not used. Operation is synchronous with the input clock. Table 10-4-8 SMR Settings and SCI3 Communication Format SMR Setting Bit7 Bit6 Bit2 Bit5 Bit3 COM CHR MP PE STOP Mode 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 * * 1 * * 1 * 0 * 0 1 0 1 * Synchronous mode 8-bit data No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Asynchronous mode Communication Format MultiproData Length cessor Bit 8-bit data No Parity Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Note: * Don't care 292 Table 10-4-9 SMR and SCR3 Settings and Clock Source Selection SMR Bit7 COM 0 SCR3 Bit1 Bit0 CKE1 CKE0 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 0 1 1 1 Synchronous mode Reserved Mode Asynchronous mode Clock Source Internal External Internal External Transmit/Receive Clock Pin SCK3 Function I/O port (SCK3 function not used) Outputs clock with same frequency as bit rate Clock should be input with frequency 16 times the desired bit rate Outputs a serial clock Inputs a serial clock (illegal settings) 3. Continuous transmit/receive operation using interrupts Continuous transmit and receive operations are possible with SCI3, using the RXI or TXI interrupts. Table 10-4-10 explains this use of these interrupts. Table 10-4-10 Transmit/Receive Interrupts Interrupt RXI Flag RDRF RIE Interrupt Conditions When serial data is received normally and receive data is transferred from RSR to RDR, RDRF is set to 1. If RIE is 1 at this time, RXI is enabled and an interrupt occurs. (See figure 10-4-2 (a).) When TSR empty (previous transmission complete) is detected and the transmit data set in TDR is transferred to TSR, TDRE is set to 1. If TIE is 1 at this time, TXI is enabled and an interrupt occurs. (See figure 10-4-2 (b).) When the last bit of the TSR transmit character has been sent, if TDRE is 1, then 1 is set in TEND. If TEIE is 1 at this time, TEI is enabled and an interrupt occurs. (See figure 10-4-2 (c).) Remarks The RXI interrupt handler routine should read the receive data from RDR and clear RDRF to 0. Continuous receiving is possible if these operations are completed before the next data has been completely received in RSR. The TXI interrupt handler routine should write the next transmit data to TDR and clear TDRE to 0. Continuous transmission is possible if these operations are completed before the data transferred to TSR has been completely transmitted. TEI indicates that, when the last bit of the TSR transmit character was sent, the next transmit data had not been written to TDR. TXI TDRE TIE TEI TEND TEIE 293 RDR RDR RSR (receiving) RXD pin RDRF = 0 RXD pin RSR (received and transferred) RDRF 1 (RXI requested if RIE = 1) Figure 10-4-2 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TDR TSR (transmitting) TXD pin TDRE = 0 TXD pin TSR (transmission complete, next data transferred) TDRE 1 (TXI requested if TIE = 1) Figure 10-4-2 (b) TDRE Setting and TXI Interrupt TDR TDR TSR (transmitting) TXD pin TEND = 0 TXD pin TSR (transmission end) TEND 1 (TEI requested if TEIE = 1) Figure 10-4-2 (c) TEND Setting and TEI Interrupt 294 10.4.4 Operation in Asynchronous Mode In asynchronous communication mode, a start bit indicating the start of communication and a stop bit (1 or 2 bits) indicating the end of communication are added to each character that is sent. In this way synchronization is achieved for each character as a self-contained unit. SCI3 consists of independent transmit and receive modules, giving it the capability of full duplex communication. Both the transmit and receive modules have a double-buffer configuration, allowing data to be read or written during communication operations so that data can be transmitted and received continuously. 1. Transmit/receive formats Figure 10-4-3 shows the general format for asynchronous serial communication. The communication line in asynchronous communication mode normally stays at the high level, in the "mark" state. SCI3 monitors the communication line, and begins serial data communication when it detects a "space" (low-level signal), which is regarded as a start bit. One character consists of a start bit (low level), transmit/receive data (in LSB-first order), a parity bit (high or low level), and finally a stop bit (high level), in this order. In asynchronous data receiving, synchronization is with the falling edge of the start bit. SCI3 samples data on the 8th pulse of a clock that has 16 times the frequency of the bit rate, so each bit of data is latched at its center. (LSB) Serial data Start bit Transmit or receive data (MSB) Parity bit 1 bit or none Stop bit 1 Mark state 1 bit 7 or 8 bits One unit of data (character or frame) 1 or 2 bits Figure 10-4-3 Data Format in Asynchronous Serial Communication Mode 295 Table 10-4-11 shows the 12 formats that can be selected in asynchronous mode. The format is selected in the serial mode register (SMR). Table 10-4-11 Serial Communication Formats in Asynchronous Mode SMR Setting CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 * * * * MP STOP 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S Serial Communication Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB STOP MPB STOP STOP MPB STOP MPB STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data Start bit Notation: S: STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Note: * Don't care 296 2. Clock The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10-4-9 for the settings. Either an internal clock source can be used to run the built-in baud rate generator, or an external clock source can be input at pin SCK3. When an external clock source is input, it should have a frequency 16 times the desired bit rate. When an internal clock source is used, SCK3 is used as the clock output pin. The clock output has the same frequency as the serial bit rate, and is synchronized as in figure 10-4-4 so that the rising edge of the clock occurs in the center of each bit of transmit/receive data. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (1 frame) Figure 10-4-4 Phase Relation of Output Clock and Communication Data in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 2 Stop Bits) 3. * Data transmit/receive operations SCI3 initialization Before data is sent or received, bits TE and RE in serial control register 3 (SCR3) must be cleared to 0, after which initialization can be performed using the procedure shown in figure 10-4-5. Note: When modifying the operation mode, transfer format or other settings, always be sure to clear bits TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing RE does not clear the status flags RDRF, PER, FER, or OER, or alter the contents of the receive data register (RDR). When an external clock is used in asynchronous mode, do not stop the clock during operation, including during initialization. When an external clock is used in synchronous mode, do not supply the clock during initialization. 297 Figure 10-4-5 shows a typical flow chart for SCI3 initialization. Start Clear TE and RE to 0 in SCR3 1 Set bits CKE1 and CKE0 2 Select communication format in SMR 1. Select the clock in serial control register 3 (SCR3). If clock output is selected in asynchronous mode, a clock signal will be output as soon as CKE1 and CKE2 have been set. During reception in synchronous mode, if clock output is selected by bits CKE1 and CKE0, a clock signal will be output as soon as RE is set to 1. 2. Set the transmit/receive format in the serial mode register (SMR). 3 Set BRR value Wait Has a 1-bit interval elapsed? Yes 4 Set bits RIE, TIE, TEIE, and MPIE in SCR3, and set TE or RE to 1 No 3. Set the bit rate register (BRR) to the value giving the desired bit rate. This step is not required when an external clock source is used. 4. Wait for at least a 1-bit interval, then set bits RIE, TIE, TEIE, and MPIE, and set bit TE or RE in SCR3 to 1. Setting TE or RE enables SCI3 to use the TXD or RXD pin. The initial states in asynchronous mode are the mark transmit state and the idle receive state (waiting for a start bit). End Figure 10-4-5 Typical Flow Chart when SCI3 Is Initialized 298 * Transmitting Figure 10-4-6 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR TDRE = 1? Yes Write transmit data in TDR No 1. Read the serial status register (SRR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. 2 Continue data transmission? No Read bit TEND in SSR Yes 2. To continue transmitting data, read bit TDRE to make sure it is set to 1, then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. No TEND = 1? Yes 3 Break output? Yes Set PDR = 0 and PCR = 1 No 3. To output a break signal when transmission ends, first set the port values PCR = 1 and PDR = 0, then clear bit TE in SCR3 to 0. Clear bit TE in SCR3 to 0 End Figure 10-4-6 Typical Data Transmission Flow Chart (Asynchronous Mode) 299 SCI3 operates as follows during data transmission in asynchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. Serial data is transmitted from pin TXD using the communication format outlined in table 10-4-11. Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1. Figure 10-4-7 shows a typical operation in asynchronous transmission mode. Start bit Serial data 1 0 D0 Transmit data D1 D7 1 frame Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 D7 1 frame Parity Stop Mark bit bit state 0/1 1 1 TDRE TEND SCI3 TXI request TDRE cleared to 0 operation User processing Write data in TDR TXI request TEI request Figure 10-4-7 Typical Transmit Operation in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 1 Stop Bit) 300 * Receiving Figure 10-4-8 shows a typical flow chart for receiving serial data. After SCI3 initialization, follow the procedure below. Start 1. Read bits OER, PER, and FER in the serial status register (SSR) to determine if a receive error has occurred. If a receive error has occurred, receive error processing is executed. 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read received data from the receive data register (RDR). When RDR data is read, RDRF is automatically cleared to 0. 3. To continue receiving data, read bit RDRF and finish reading RDR before the stop bit of the present frame is received. When data is read from RDR, RDRF is automatically cleared to 0. 4. When a receive error occurs, read bits OER, PER, and FER in SSR to determine which error (s) occurred. After the necessary error processing, be sure to clear the above bits all to 0. Data receiving cannot be resumed while any of bits OER, PER, or FER is set to 1. When a framing error occurs, a break can be detected by reading the RXD pin value. Yes Break? No Yes PER = 1? No Clear bits OER, PER, and FER in SSR to 0 End receive error processing Parity error processing A Framing error processing 1 Read bits OER, PER, and FER in SSR OER + PER + FER = 1 No Yes 2 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Receive error processing Yes 3 Continue receiving? No A Clear bit RE in SCR3 to 0 End 4 Start receive error processing Yes OER = 1? No Yes FER = 1? No Overrun error processing Figure 10-4-8 Typical Serial Data Receiving Flow Chart in Asynchronous Mode 301 SCI3 operates as follows when receiving serial data in asynchronous mode. SCI3 monitors the communication line, and when a start bit (0) is detected it performs internal synchronization and starts receiving. The communication format for data receiving is as outlined in table 10-4-11. Received data is set in RSR from LSB to MSB, then the parity bit and stop bit(s) are received. After receiving the data, SCI3 performs the following checks: * Parity check: The number of 1s received is checked to see if it matches the odd or even parity selected in bit PM of SMR. Stop bit check: The stop bit is checked for a value of 1. If there are two stop bits, only the first bit is checked. Status check: The RDRF bit is checked for a value of 0 to make sure received data can be transferred from RSR to RDR. * * If no receive error is detected by the above checks, bit RDRF is set to 1 and the received data is stored in RDR. At that time, if bit RIE in SCR3 is set to 1, an RXI interrupt is requested. If the error check detects a receive error, the appropriate error flag (OER, PER, or FER) is set to 1. RDRF retains the same value as before the data was received. If at this time bit RIE in SCR3 is set to 1, an ERI interrupt is requested. Table 10-4-12 gives the receive error detection conditions and the processing of received data in each case. Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0. Table 10-4-12 Receive Error Conditions and Received Data Processing Receive Error Overrun error Framing error Parity error Abbrev. OER FER PER Detection Conditions Received Data Processing Receiving of the next data ends while Received data is not bit RDRF in SSR is still set to 1 transferred from RSR to RDR Stop bit is 0 Received data does not match the parity (odd/even) set in SMR Received data is transferred from RSR to RDR Received data is not transferred from RSR to RDR 302 Figure 10-4-9 shows a typical SCI3 data receive operation in asynchronous mode. Start bit Serial 1 data 0 D0 Receive data D1 D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark (idle state) 1 1 frame RDRF FER SCI3 operation RXI request RDRF cleared to 0 Read RDR data Detects stop bit = 0 ERI request due to framing error Framing error handling User processing Figure 10-4-9 Typical Receive Operation in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 1 Stop Bit) 10.4.5 Operation in Synchronous Mode In synchronous mode, data is sent or received in synchronization with clock pulses. This mode is suited to high-speed serial communication. SCI3 consists of independent transmit and receive modules, so full duplex communication is possible, sharing the same clock between both modules. Both the transmit and receive modules have a double-buffer configuration. This allows data to be written during a transmit operation so that data can be transmitted continuously, and enables data to be read during a receive operation so that data can be received continuously. 1. Transmit/receive format Figure 10-4-10 shows the general communication data format for synchronous communication. 303 * Serial clock LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 * Don't care 8 bits One unit of communication data (character or frame) Note: * At high level except during continuous transmit/receive. Figure 10-4-10 Data Format in Synchronous Communication Mode In synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. Data is guaranteed valid at the rising edge of the serial clock. One character of data starts from the LSB and ends with the MSB. The communication line retains the MSB state after the MSB is output. In synchronous receive mode, SCI3 latches receive data in synchronization with the rising edge of the serial clock. The transmit/receive format is fixed at 8-bit data. No parity bit or multiprocessor bit is added in this mode. 2. Clock Either an internal clock from the built-in baud rate generator is used, or an external clock is input at pin SCK3. The choice of clock sources is designated by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10-4-9 for details on selecting the clock source. When operation is based on an internal clock, a serial clock is output at pin SCK3. Eight clock pulses are output per character of transmit/receive data. When no transmit or receive operation is being performed, the pin is held at the high level. 304 3. * Data transmit/receive operations SCI3 initialization Before transmitting or receiving data, follow the SCI3 initialization procedure explained under 10.4.4, SCI3 Initialization, and illustrated in figure 10-4-5. * Transmitting Figure 10-4-11 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR No TDRE = 1? Yes Write transmit data in TDR 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0 and data transmission begins. If clock output has been selected, after data is written to TDR, the clock is output and data transmission begins. Yes 2 Continue data transmission? No 2. To continue transmitting data, read bit TDRE to make sure it is set to 1, then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. Read bit TEND in SSR TEND = 1? Yes No Write 0 to bit TE in SCR3 End Figure 10-4-11 Typical Data Transmission Flow Chart in Synchronous Mode 305 SCI3 operates as follows during data transmission in synchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. If clock output is selected, SCI3 outputs eight serial clock pulses. If an external clock is used, data is output in synchronization with the clock input. Serial data is transmitted from pin TXD in order from LSB (bit 0) to MSB (bit 7). Then TDRE is checked as the MSB (bit 7) is being transmitted. If TDRE is 0, data is transferred from TDR to TSR, and after the MSB (bit 7) is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the MSB (bit 7) has been sent, the MSB state is maintained. A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1. After data transmission ends, pin SCK3 is held at the high level. Note: Data transmission cannot take place while any of the receive error flags (OER, FER, PER) is set to 1. Be sure to confirm that these error flags are cleared to 0 before starting transmission. Figure 10-4-12 shows a typical SCI3 transmit operation in synchronous mode. Serial clock Serial data Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 TDRE TEND SCI3 operation User processing TXI request TDRE cleared to 0 Write data in TDR TXI request TEI request Figure 10-4-12 Typical SCI3 Transmit Operation in Synchronous Mode 306 * Receiving Figure 10-4-13 shows a typical flow chart for receiving data. After SCI3 initialization, follow the procedure below. Start 1 Read bit OER in SSR Yes OER = 1? No 1. Read bit OER in the serial status register (SSR) to determine if an error has occurred. If an overrun error has occurred, overrun error processing is executed. 2 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Overrun error processing Continue receiving? No Clear bit RE in SCR3 to 0 Yes 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read received data from the receive data register (RDR). When data is read from RDR, RDRF is automatically cleared to 0. 3. To continue receiving data, read bit RDRF and read the received data in RDR before the MSB (bit 7) of the present frame is received. When data is read from RDR, RDRF is automatically cleared to 0. 3 End Start overrun processing Overrun error processing Clear bit OER in SSR to 0 End overrun error processing 4. When an overrun error occurs, read bit OER in SSR. After the necessary error processing, be sure to clear OER to 0. Data receiving cannot be resumed while bit OER is set to 1. 4 Figure 10-4-13 Typical Data Receiving Flow Chart in Synchronous Mode 307 SCI3 operates as follows when receiving serial data in synchronous mode. SCI3 synchronizes internally with the input or output of the serial clock and starts receiving. Received data is set in RSR from LSB to MSB. After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating that received data can be transferred from RSR to RDR. If this check passes, RDRF is set to 1 and the received data is stored in RDR. At this time, if bit RIE in SCR3 is set to 1, an RXI interrupt is requested. If an overrun error is detected, OER is set to 1 and RDRF remains set to 1. Then if bit RIE in SCR3 is set to 1, an ERI interrupt is requested. For the overrun error detection conditions and receive data processing, see table 10-4-12. Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0. Figure 10-4-14 shows a typical receive operation in synchronous mode. Serial clock Serial data Bit 7 Bit 0 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 RDRF OER SCI3 operation User processing RXI request RDRF cleared to 0 Read data from RDR RXI request RDR data not read (RDRF = 1) ERI request due to overrun error Overrun error handling Figure 10-4-14 Typical Receive Operation in Synchronous Mode 308 * Simultaneous transmit/receive Figure 10-4-15 shows a typical flow chart for transmitting and receiving simultaneously. After SCI3 synchronization, follow the procedure below. Start 1 Read bit TDRE in SSR No TDRE = 1? Yes 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read the received data from the receive data register (RDR). When data is read from RDR, RDRF is automatically cleared to 0. 3. To continue transmitting and receiving serial data, read bit RDRF and finish reading RDR before the MSB (bit 7) of the present frame is received. Also read bit TDRE, check that it is set to 1, and write the next data in TDR before the MSB of the current frame has been transmitted. When data is written to TDR, TDRE is automatically cleared to 0; and when data is read from RDR, RDRF is automatically cleared to 0. 4. When an overrun error occurs, read bit OER in SSR. After the necessary error processing, be sure to clear OER to 0. Data transmission and reception cannot take place while bit OER is set to 1. See figure 10-4-13 for overrun error processing. 2 Write transmit data in TDR Read bit OER in SSR Yes OER = 1? No Read RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Continue transmitting and receiving? No Clear bits TE and RE in SCR3 to 0 End Overrun error processing Yes 3 Figure 10-4-15 Simultaneous Transmit/Receive Flow Chart in Synchronous Mode 309 Notes: 1. To switch from transmitting to simultaneous transmitting and receiving, use the following procedure. * First confirm that TDRE and TEND are both set to 1 and that SCI3 has finished transmitting. Next clear TE to 0. Then set both TE and RE to 1. 2. To switch from receiving to simultaneous transmitting and rceiving, use the following procedure. * After confirming that SCI3 has finished receiving, clear RE to 0. Next, after confirming that RDRF and the error flags (OER FER, PER) are all 0, set both TE and RE to 1. 10.4.6 Multiprocessor Communication Function The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID code. A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit is 1 in an ID-sending cycle, and 0 in a data-sending cycle. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. When a receiving processor receives data with the multiprocessor bit set to 1, it compares the data with its own ID. If the data matches its ID, the receiving processor continues to receive incoming data. If the data does not match its ID, the receiving processor skips further incoming data until it again receives data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 10-4-16 shows an example of communication among different processors using a multiprocessor format. 310 Transmitting processor Communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-sending cycle (receiving processor address) H'AA (MPB = 0) Data-sending cycle (data sent to receiving processor designated by ID) MPB: Multiprocessor bit Figure 10-4-16 Example of Interprocessor Communication Using Multiprocessor Format (Data H'AA Sent to Receiving Processor A) Four communication formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 10-4-11. For a description of the clock used in multiprocessor communication, see 10.4.4, Operation in Asynchronous Mode. 311 * Transmitting multiprocessor data Figure 10-4-17 shows a typical flow chart for multiprocessor serial data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR No Yes Set bit MPBT in SSR TDRE = 1? 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, set bit MPBT (multiprocessor bit transmit) in SSR to 0 or 1, then write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. Write transmit data to TDR 2 Continue transmitting? No Yes Read bit TEND in SSR 2. To continue transmitting data, read bit TDRE to make sure it is set to 1, then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. TEND = 1? Yes 3 Break output? Yes Set PDR = 0 and PCR = 1 No No 3. To output a break signal at the end of data transmission, first set the port values PCR = 1 and PDR = 0, then clear bit TE in SCR3 to 0. Clear bit TE in SCR3 to 0 End Figure 10-4-17 Typical Multiprocessor Data Transmission Flow Chart 312 SCI3 operates as follows during data transmission using a multiprocessor format. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. Serial data is transmitted from pin TXD using the communication format outlined in table 10-4-11. Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE (transmit end interrupt enable) in SCR3 is set to 1. Figure 10-4-18 shows a typical SCI3 operation in multiprocessor communication mode. Start bit Serial data 1 0 D0 Transmit data D1 D7 MPB 0/1 Stop Start bit bit 1 0 D0 Transmit data D1 D7 MPB 0/1 Stop Mark state bit 1 1 1 frame TDRE TEND 1 frame SCI3 TXI request operation User processing TDRE cleared to 0 Write data in TDR TXI request TEI request Figure 10-4-18 Typical Multiprocessor Format Transmit Operation (8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit) 313 * Receiving multiprocessor data Figure 10-4-19 shows a typical flow chart for receiving data using a multiprocessor format. After SCI3 initialization, follow the procedure below. Start 1 2 Set bit MPIE in SCR3 to 1 Read bits OER and FER in SSR Yes OER + FER = 1? 3 No Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR Own ID? Yes Read bits OER and FER in SSR OER + FER = 1? No 4 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 5 Error processing Yes Continue receiving? No Clear bit RE in SCR3 to 0 OER = 1? End No Yes FER = 1? No Clear bits OER and FER in SSR to 0. End receive error processing No Framing error processing A Break? Yes A Start receive error processing Yes Overrun error processing Yes No 5. If a receive error occurs, read bits OER and FER in SSR to determine which error occurred. After the necessary error processing, be sure to clear the error flags to 0. Serial data transfer cannot take place while bit OER or FER is set to 1. When a framing error occurs, a break can be detected by reading the RXD pin value. 1. Set bit MPIE in serial control register 3 (SCR3) to 1. 2. Read bits OER and FER in the serial status register (SSR) to determine if an error has occurred. If a receive error has occurred, receive error processing is executed. 3. Read the serial status register (SSR) and confirm that RDRF = 1. If RDRF = 1, read the data in the received data register (RDR) and compare it with the processor's own ID. If the received data does not match the ID, set bit MPIE to 1 again. Bit RDRF is automatically cleared to 0 when data in the received data register (RDR) is read. 4. Read SSR, check that bit RDRF = 1, then read received data from the receive data register (RDR). Figure 10-4-19 Typical Flow Chart for Receiving Serial Data Using Multiprocessor Format 314 Figure 10-4-20 gives an example of data reception using a multiprocessor format. Start bit Serial data 1 0 D0 Receive data (ID1) D1 D7 Stop Start bit MPB bit 1 1 0 D0 Receive data (data 1) D1 D7 Stop MPB bit 0 1 Mark (idle state) 1 1 frame MPIE RDRF RDR value SCI3 operation User processing RXI request MPIE cleared to 0 RDRF cleared to 0 Read data from RDR 1 frame ID1 No RXI request RDR state retained If not own ID, set MPIE to 1 again (a) Data does not match own ID Start bit Serial data 1 0 D0 Receive data (ID2) D1 D7 Stop Start MPB bit bit 1 1 0 D0 Receive data (data 2) D1 D7 Stop MPB bit 0 1 Mark (idle state) 1 1 frame MPIE RDRF RDR value SCI3 operation 1 frame ID1 RXI request MPIE cleared to 0 RDRF cleared to 0 ID2 RDRF cleared to 0 If own ID, continue receiving RXI request Data 2 User processing Read data from RDR Read data from RDR and set MPIE to 1 again (b) Data matches own ID Figure 10-4-20 Example of Multiprocessor Format Receive Operation (8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit) 315 10.4.7 Interrupts SCI3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three receive error interrupts (overrun error, framing error, and parity error). All share a common interrupt vector. Table 10-4-13 describes each interrupt. Table 10-4-13 SCI3 Interrupts Interrupt RXI TXI TEI ERI Description Interrupt request due to receive data register full (RDRF) Interrupt request due to transmit data register empty (TDRE) Interrupt request due to transmit end (TEND) Interrupt request due to receive error (OER, FER, or PER) Vector Address H'0024 The interrupt requests are enabled and disabled by bits TIE and RIE of SCR3. When bit TDRE in SSR is set to 1, TXI is requested. When bit TEND in SSR is set to 1, TEI is requested. These two interrupt requests occur during data transmission. The initial value of bit TDRE is 1. Accordingly, if the transmit data empty interrupt request (TXI) is enabled by setting bit TIE to 1 in SCR3 before placing transmit data in TDR, TXI will be requested even though no transmit data has been readied. Likewise, the initial value of bit TEND is 1. Accordingly, if the transmit end interrupt request (TEI) is enabled by setting bit TEIE to 1 in SCR3 before placing transmit data in TDR, TEI will be requested even though no data has been transmitted. These interrupt features can be used to advantage by programming the interrupt handler to move the transmit data into TDR. When this technique is not used, the interrupt enable bits (TIE and TEIE) should not be set to 1 until after TDR has been loaded with transmit data, to avoid unwanted TXI and TEI interrupts. When bit RDRF in SSR is set to 1, RXI is requested. When any of SSR bits OER, FER, or PER is set to 1, ERI is requested. These two interrupt requests occur during the receiving of data. Details on interrupts are given in 3.3, Interrupts. 316 10.4.8 Application Notes When using SCI3, attention should be paid to the following matters. 1. Relation between bit TDRE and writing data to TDR Bit TDRE in the serial status register (SSR) is a status flag indicating that TDR does not contain new transmit data. TDRE is automatically cleared to 0 when data is written to TDR. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR regardless of the status of bit TDRE. However, if new data is written to TDR while TDRE is cleared to 0, assuming the data held in TDR has not yet been shifted to TSR, it will be lost. For this reason it is advisable to confirm that bit TDRE is set to 1 before each write to TDR and not write to TDR more than once without checking TDRE in between. 2. Operation when multiple receive errors occur at the same time When two or more receive errors occur at the same time, the status flags in SSR are set as shown in table 10-4-14. If an overrun error occurs, data is not transferred from RSR to RDR, and receive data is lost. Table 10-4-14 SSR Status Flag States and Transfer of Receive Data SSR Status Flags RDRF* OER 1 0 0 1 1 0 1 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 x x x Receive Data Transfer (RSR RDR) Receive Error Status x Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data transferred from RSR to RDR x: Receive data not transferred from RSR to RDR Note: * RDRF keeps the same state as before the data was received. However, if due to a late read of received data in one frame an overrun error occurs in the next frame, RDRF is cleared to 0 when RDR is read. Notation: 317 3. Break detection and processing Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state SCI3 continues to receive, so if the FER bit is cleared to 0 it will be set to 1 again. 4. Sending a mark or break signal When TE is cleared to 0 the TXD pin becomes an I/O port, the level and direction (input or output) of which are determined by the PDR and PCR bits. This feature can be used to place the TXD pin in the mark state or send a break signal. To place the serial communication line in the mark (1) state before TE is set to 1, set the PDR and PCR bits both to 1. Since TE is cleared to 0, TXD becomes a general output port outputting the value 1. To send a break signal during data transmission, set the PCR bit to 1 and clear the PDR bit to 0, then clear TE to 0. When TE is cleared to 0 the transmitter is initialized, regardless of its current state, so the TXD pin becomes an output port outputting the value 0. 5. Receive error flags and transmit operation (sysnchronous mode only) When a receive error flag (ORER, PER, or FER) is set to 1, SCI3 will not start transmitting even if TDRE is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. 6. Receive data sampling timing and receive margin in asynchronous mode In asynchronous mode SCI3 operates on a base clock with 16 times the bit rate frequency. In receiving, SCI3 synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure 10-4-21. 318 16 clock cycles 8 clock cycles Internal base clock 0 7 15 0 7 15 0 Receive data (RXD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 10-4-21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be derived from the following equation. M = {(0.5 - 1/2N) - (D - 0.5) / N - (L - 0.5) F} x 100% ....................................Equation (1) M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0.5 to 1) Frame length (L = 9 to 12) Absolute value of clock frequency error In equation (1), if F (absolute value of clock frequency error) = 0 and D (clock duty cycle) = 0.5, the receive margin is 46.875% as given by equation (2) below. When D = 0.5 and F = 0, M = {0.5 - 1/(2 x 16)} x 100% = 46.875% ..........................................................Equation (2) This value is theoretical. In actual system designs a margin of from 20 to 30 percent should be allowed. 319 7. Relationship between bit RDRF and reading RDR While SCI3 is receiving, it checks the RDRF flag. When a frame of data has been received, if the RDRF flag is cleared to 0, data receiving ends normally. If RDRF is set to 1, an overrun error occurs. RDRF is automatically cleared to 0 when the contents of RDR are read. If RDR is read more than once, the second and later reads will be performed with RDRF cleared to 0. While RDRF is 0, if RDR is read when reception of the next frame is just ending, data from the next frame may be read. This is illustrated in figure 10-4-22. Frame 1 Frame 2 Frame 3 Communication line Data 1 Data 2 Data 3 RDRF RDR Data 1 A B Data 2 User processing RDR read RDR read At A , data 1 is read. At B , data 2 is read. Figure 10-4-22 Relationship between Data and RDR Read Timing To avoid the situation described above, after RDRF is confirmed to be 1, RDR should only be read once and should not be read twice or more. When the same data must be read more than once, the data read the first time should be copied to RAM, for example, and the copied data should be used. An alternative is to read RDR but leave a safe margin of time before reception of the next frame is completed. In synchronous mode, all reads of RDR should be completed before bit 7 is received. In asynchronous mode, all reads of RDR should be completed before the stop bit is received. 320 8. Switching SCK3 function If pin SCK3 is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock () cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. a. When an SCK3 function is switched from clock output to non clock-output When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents SCK3 from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to SCK3, the line connected to SCK3 should be pulled up to the Vcc level via a resistor, or supplied with output from an external device. b. When an SCK3 function is switched from clock output to general input/output When stopping data transfer, (i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. (ii) Clear bit COM in SCR3 to 0 (iii) Clear bits CKE1 and CKE0 in SCR3 to 0 Note that special care is also needed here to avoid an intermediate level of voltage from being applied to SCK3. 9. Switching TXD function If pin TXD is used as a data output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a high level signal for one system clock () cycle immediately after it is switched. 321 Section 11 14-Bit PWM 11.1 Overview The H8/3834U Series is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a D/A converter by connecting a low-pass filter. 11.1.1 Features Features of the 14-bit PWM are as follows. * Choice of two conversion periods A conversion period of 32,768/o, with a minimum modulation width of 2/o (PWCR0 = 1), or a conversion period of 16,384/o, with a minimum modulation width of 1/o (PWCR0 = 0), can be chosen. * Pulse division method for less ripple 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the 14-bit PWM. PWDRL o/2 o/4 PWM waveform generator PWCR PWM Notation: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register Figure 11-1 Block Diagram of the 14 bit PWM 323 Internal data bus PWDRU 11.1.3 Pin Configuration Table 11-1 shows the output pin assigned to the 14-bit PWM. Table 11-1 Pin Configuration Name PWM output pin Abbrev. PWM I/O Output Function Pulse-division PWM waveform output 11.1.4 Register Configuration Table 11-2 shows the register configuration of the 14-bit PWM. Table 11-2 Register Configuration Name PWM control register PWM data register U PWM data register L Abbrev. PWCR PWDRU PWDRL R/W W W W Initial Value H'FE H'C0 H'00 Address H'FFD0 H'FFD1 H'FFD2 324 11.2 Register Descriptions 11.2.1 PWM Control Register (PWCR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PWCR0 0 W PWCR is an 8-bit write-only register for input clock selection. Upon reset, PWCR is initialized to H'FE. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved; they are always read as 1, and cannot be modified. Bit 0: Clock select 0 (PWCR0) Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a write-only bit; it is always read as 1. Bit 0 PWCR0 Description 0 1 The input clock is o/2 (to = 2/o). The conversion period is 16,384/o, with a minimum modulation width of 1/o. (initial value) The input clock is o/4 (to = 4/o). The conversion period is 32,768/o, with a minimum modulation width of 2/o. Notation: to: Period of PWM input clock 325 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU Bit Initial value Read/Write PWDRL Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle. When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should always be written in the following sequence, first to PWDRL and then to PWDRU. 1. 2. Write the lower 8 bits to PWDRL. Write the upper 6 bits to PWDRU. PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1. Upon reset, PWDRU and PWDRL are initialized to H'C000. 326 11.3 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P14/PWM is designated for PWM output. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32,768/o (PWCR0 = 1) or 16,384/o (PWCR0 = 0). Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data in these registers will be latched in the PWM waveform generator, updating the PWM waveform generation in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 11-2. The total of the highlevel pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be represented as follows. TH = (data value in PWDRU and PWDRL + 64) x to/2 where to is the PWM input clock period, either 2/o (bit PWCR0 = 0) or 4/o (bit PWCR0 = 1). Example: Settings in order to obtain a conversion period of 8,192 s: When bit PWCR0 = 0, the conversion period is 16,384/o, so o must be 2 MHz. In this case tfn = 128 s, with 1/o (resolution) = 0.5 s. When bit PWCR0 = 1, the conversion period is 32,768/o, so o must be 4 MHz. In this case tfn = 128 s, with 2/o (resolution) = 0.5 s. Accordingly, for a conversion period of 8,192 s, the system clock frequency (o) must be 2 MHz or 4 MHz. 2. 3. 327 1 conversion period t f1 t f2 t f63 t f64 t H1 t H2 t H3 t H63 t H64 TH = t H1 + t H2 + t H3 + ..... t H64 t f1 = t f2 = t f3 ..... = t f84 Figure 11-2 PWM Output Waveform 328 Section 12 A/D Converter 12.1 Overview The H8/3834U Series includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 12 channels of analog input. 12.1.1 Features The A/D converter has the following features. * * * * * * 8-bit resolution 12 input channels Conversion time: approx. 12.4 s per channel (at 5 MHz operation) Built-in sample-and-hold function Interrupt requested on completion of A/D conversion A/D conversion can be started by external trigger input 12.1.2 Block Diagram Figure 12-1 shows a block diagram of the A/D converter. ADTRG AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 AN 8 AN 9 AN 10 AN 11 A/D mode register AVCC + Comparator - Reference voltage AVSS A/D result register Control logic AVCC AVSS Figure 12-1 Block Diagram of the A/D Converter 329 Internal data bus IRRAD Multiplexer A/D start register 12.1.3 Pin Configuration Table 12-1 shows the A/D converter pin configuration. Table 12-1 Pin Configuration Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 External trigger input pin Abbrev. AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 Analog input channel 8 Analog input channel 9 Analog input channel 10 Analog input channel 11 External trigger input for starting A/D conversion 12.1.4 Register Configuration Table 12-2 shows the A/D converter register configuration. Table 12-2 Register Configuration Name A/D mode register A/D start register A/D result register Abbrev. AMR ADSR ADRR R/W R/W R/W R Initial Value H'30 H'7F Not fixed Address H'FFC4 H'FFC6 H'FFC5 330 12.2 Register Descriptions 12.2.1 A/D Result Register (ADRR) Bit Initial value Read/Write 7 ADR7 -- R 6 ADR6 -- R 5 ADR5 -- R 4 ADR4 -- R 3 ADR3 -- R 2 ADR2 -- R 1 ADR1 -- R 0 ADR0 -- R The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-todigital conversion. ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data is held in ADRR until the next conversion operation starts. ADRR is not cleared on reset. 12.2.2 A/D Mode Register (AMR) Bit Initial value Read/Write 7 CKS 0 R/W 6 TRGE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger option, and the analog input pins. Upon reset, AMR is initialized to H'30. Bit 7: Clock select (CKS) Bit 7 sets the A/D conversion speed. Bit 7 CKS 0 1 Conversion Time Conversion Period 62/o (initial value) 31/o o = 2 MHz 31 s 15.5 s o = 5 MHz 12.4 s * Note: * Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a value of at least 12.4 s. 331 Bit 6: External trigger select (TRGE) Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6 TRGE 0 1 Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of the IRQ edge select register (IEGR). See 3.3.2 for details. Bits 5 and 4: Reserved bits Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. Bits 3 to 0: Channel select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3 CH3 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 CH2 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 CH1 * 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 CH0 * 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel No channel selected AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 (initial value) Note: * Don't care 332 12.2.3 A/D Start Register (ADSR) Bit Initial value Read/Write 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared to 0. Bit 7: A/D start flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF 0 Description Read Write 1 Read Write Indicates the completion of A/D conversion Stops A/D conversion Indicates A/D conversion in progress Starts A/D conversion (initial value) Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 333 12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is set to 1. If the conversion time or input channel needs to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 Start of A/D Conversion by External Trigger Input The A/D converter can be made to start A/D conversion by input of an external trigger signal. External trigger input is enabled at pin ADTRG when bit IRQ4 in port mode register 2 (PMR2) is set to 1, and bit TRGE in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of the IRQ edge select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion. Figure 12-2 shows the timing. o Pin ADTRG (when bit IEG4 = 0) ADSF A/D conversion Figure 12-2 External Trigger Input Timing 334 12.4 Interrupts When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2). For further details see 3.3, Interrupts. 12.5 Typical Use An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 12-3 shows the operation timing. * Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D converter goes to the idle state. Bit IENAD = 1, so an A/D conversion end interrupt is requested. The A/D interrupt handling routine starts. The A/D conversion result is read and processed. The A/D interrupt handling routine ends. * * * * * If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12-4 and 12-5 show flow charts of procedures for using the A/D converter. 335 Interrupt (IRRAD) Set * IENAD ADSF A/D conversion starts Set * Set * Figure 12-3 Typical A/D Converter Operation Timing 336 Idle A/D conversion (1) Idle A/D conversion result (1) Channel 1 (AN 1) operation state A/D conversion (2) Idle Read conversion result Read conversion result A/D conversion result (2) ADRR Note: * ( ) indicates instruction execution by software. Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRR data Yes Perform A/D conversion? No End Figure 12-4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software) 337 Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? No Yes Clear bit IRRAD to 0 in IRR2 Read ADRR data Yes Perform A/D conversion? No End Figure 12-5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 12.6 Application Notes * Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. * 338 Section 13 LCD Controller/Driver 13.1 Overview The H8/3834U Series has an on-chip segment-type LCD controller circuit, LCD driver, and power supply circuit, for direct driving of an LCD panel. 13.1.1 Features Features of the LCD controller/driver are as follows. * Display capacity Duty On-chip driver only Use with external segment expansion driver -- Static 1/2 1/3 1/4 Internal Driver 40 segments 36 segments 36 segments 36 segments 36 segments External Segment Expansion Driver 0 476 segments 220 segments 92 segments 92 segments The HD66100 can be used for external expansion of the number of segments. * LCD RAM capacity 8 bits x 64 bytes (512 bits) * * * Word access to LCD RAM Segment output pins can be switched to general-purpose ports in groups of 4 Unused common output pins can be used either for boosting common output (by parallel connection) or as ports. Displays in all operation modes except standby mode. Choice of 11 frame frequencies Internal voltage divider for liquid crystal driver power supply * * * 339 13.1.2 Block Diagram Figure 13-1 shows a block diagram of the LCD controller/driver. VCC M o/2 to o/256 oW CL2 LCD driver power supply V1 V2 V3 VSS COM 1 COM 4 SEG 40 /CL 1 SEG 39 /CL 2 SEG 38 /DO SEG 37 /M SEG 36 Common data latch Common driver LPCR LCR Internal data bus Display timing generator CL1 40-bit shift register Segment driver LCD RAM 64 bytes SEG n , DO Notation: LPCR: LCD port control register LCR: LCD control register SEG 1 Figure 13-1 LCD Controller/Driver Block Diagram 340 13.1.3 Pin Configuration Table 13-1 shows the output pins assigned to the LCD controller/driver. Table 13-1 Pin Configuration Name LCD segment output LCD common output External segment expansion signal Abbrev. SEG40 to SEG1 COM4 to COM1 CL1 CL2 M DO LCD power supply V1, V2, V3 I/O Output Output Output Output Output Output Input Function Liquid crystal segment driver pins. All pins can be programmed also as ports. Liquid crystal common driver pins. Parallel connection is possible at static and 1/2 duty. Display data latch clock; doubles as SEG40 Display data shift clock; doubles as SEG39 LCD alternating signal; doubles as SEG37 Serial display data; doubles as SEG38 For external connection to bypass capacitor or for use of external power supply circuit 13.1.4 Register Configuration Table 13-2 shows the register configuration of the LCD controller/driver. Table 13-2 Register Configuration Name LCD port control register LCD control register LCD RAM Note: * Value after reset. Abbrev. LPCR LCR -- R/W R/W R/W R/W Initial Value H'00 H'80 Not fixed Address H'FFC0 H'FFC1 H'F740 to H'F77F* 341 13.2 Register Descriptions 13.2.1 LCD Port Control Register (LPCR) Bit Initial value Read/Write 7 DTS1 0 R/W 6 DTS0 0 R/W 5 CMX 0 R/W 4 SGX 0 R/W 3 SGS3 0 R/W 2 SGS2 0 R/W 1 SGS1 0 R/W 0 SGS0 0 R/W The LCD port control register is an 8-bit read/write register, used for selecting the duty cycle and the LCD driver and pin functions, etc. Upon reset, LPCR is initialized to H'00. Bits 7 to 5: Duty and common function select (DTS1, DTS0, CMX) Bits 7 to 6 select a driver duty of static, 1/2, 1/3, or 1/4. Bit 5 determines whether the common pins not used at a given duty are to be used as ports or, in order to increase the common driving capacity, as multiple pins outputting the same waveform. Bit 7 Bit 6 Bit 5 DTS1 DTS0 CMX 0 0 0 1 0 1 0 1 1/2 duty Duty Static Common Driver*1 COM1 (initial value) COM4 to COM1 COM2 to COM1 COM4 to COM1 Other Uses COM4, COM3 and COM2 usable as ports COM4, COM3 and COM2 output the same waveform as COM1 COM4 and COM3 usable as ports COM4 outputs the same waveform as COM3, and COM2 the same waveform as COM1 COM4 usable as port COM4 outputs a non-select waveform*2 -- 1 0 0 1 1/3 duty COM3 to COM1 COM4 to COM1 COM4 to COM1 1 1 0 1 1/4 duty Notes: 1. Pins COM4 to COM1 become ports when bit SGX = 0 and bits SGS3 to SGS0 = 0000. Otherwise the common drivers are as indicated in the table above. 2. A non-select waveform is always output at pin COM4, which therefore should not be used. 342 Bit 4: Expansion signal select (SGX) Bit 4 selects whether pins SEG40/CL1, SEG39/CL2, SEG38/DO, and SEG37/M are used as segment pins (SEG40 to SEG37) or as external segment expansion pins (CL1, CL2, DO, M). Bit 4 SGX 0 1 Description Pins SEG40 to SEG37* Pins CL1, CL2, DO, M (initial value) Note: * Selected as ports when bits SGS3 to SGS0 = 0000. Bits 3 to 0: Segment driver select (SGS3 to SGS0) Bits 3 to 0 select the pins to be used as segment drivers. Functions of Pins SEG40 to SEG1 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 SEG40 to SEG36 to SEG32 to SEG28 to SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to SEG4 to SGX SGS3 SGS2 SGS1 SGS0 SEG37 SEG33 SEG29 SEG25 SEG21 SEG17 SEG13 SEG9 SEG5 SEG1 Remarks 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 * * 0 0 0 1 1 0 0 1 1 * * 0 0 1 0 1 0 1 0 1 0 1 0 Port SEG SEG SEG SEG SEG SEG SEG SEG SEG External segment expansion External segment expansion External segment expansion External segment expansion External segment expansion External segment expansion External segment expansion External segment expansion External segment expansion External segment expansion Port SEG SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG SEG Port Port Port Port Port Port Port Port SEG SEG SEG Port Port Port Port Port Port Port Port Port SEG SEG Port Port Port Port Port Port Port Port Port Port SEG Port (initial value) 1 0 0 0 1 SEG Port Port Port Port Port Port Port Port 0 0 1 0 SEG SEG Port Port Port Port Port Port Port 0 0 1 1 SEG SEG SEG Port Port Port Port Port Port 0 1 0 0 SEG SEG SEG SEG Port Port Port Port Port 0 1 0 1 SEG SEG SEG SEG SEG Port Port Port Port 0 1 1 0 SEG SEG SEG SEG SEG SEG Port Port Port 0 1 1 1 SEG SEG SEG SEG SEG SEG SEG Port Port 1 * * 0 SEG SEG SEG SEG SEG SEG SEG SEG Port 1 * * 1 SEG SEG SEG SEG SEG SEG SEG SEG SEG Note: * Don't care 343 13.2.2 LCD Control Register (LCR) Bit Initial value Read/Write 7 -- 1 -- 6 PSW 0 R/W 5 ACT 0 R/W 4 DISP 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W The LCD control register is an 8-bit read/write register for on/off control of the resistive voltage divider used as the LCD driver power supply, for display data control, and for frame frequency selection. Upon reset, LCR is initialized to H'80. Bit 7: Reserved bit Bit 7 is reserved; it is always read as 1, and cannot be modified. Bit 6: Power switch (PSW) Bit 6 switches the resistive voltage divider provided to power the LCD driver on/off. In lowpower modes when the LCD display is not used, or when an external power supply is used for the LCD, the resistive voltage divider can be switched off. When bit ACT = 0, or in standby mode, the resistive voltage divider is in the off state regardless of the bit 6 setting. Bit 6 PSW 0 1 Description LCD power supply resistive voltage divider off LCD power supply resistive voltage divider on (initial value) Bit 5: Display active (ACT) Bit 5 selects whether the LCD controller/driver is used or not. When this bit is cleared to 0, the LCD controller/driver module halts operation, and the resistive voltage divider provided for the LCD driver power supply goes to the off state regardless of the PSW setting. However, register contents are retained. Bit 5 ACT 0 1 Description LCD controller/driver operation stopped LCD controller/driver operational (initial value) 344 Bit 4: Display data control (DISP) Bit 4 selects whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. This bit is valid also when the HD66100 is used for external segment expansion. Bit 4 DISP 0 1 Description Blank data displayed LCD RAM data displayed (initial value) Bits 3 to 0: Frame frequency select (CKS3 to CKS0) Bits 3 to 0 select the clock used by the LCD controller/driver, and the frame frequency. In subactive, watch, and subsleep modes the system clock (o) is stopped, so there will be no display in these modes if o/2 to o/256 is chosen as the clock source. For display in these modes, clock oW or oW/2 must be selected. Bit 3 CKS3 0 0 0 1 1 1 1 1 1 1 1 Bit 2 CKS2 * * * 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 * 0 1 0 1 0 1 0 1 Frame Frequency*3 Clock oW oW oW/2 o/2 o/4 o/8 o/16 o/32 o/64 o/128 o/256 o = 5 MHz 128 Hz*2 64 Hz 32 Hz -- -- -- 610 Hz 305 Hz 153 Hz 76.3 Hz 38.1 Hz 610 Hz 305 Hz 153 Hz 76.3 Hz 38.1 Hz -- -- -- o = 625 kHz*1 (initial value) Notes: * Don't care 1. Frame frequency in active (medium-speed) mode 2. Only the upper 32 bytes of the display RAM are used. 3. When a duty cycle of 1/3 is chosen, the frame frequency will be 4/3 times the frequencies shown in the above table. 345 13.3 Operation 13.3.1 Settings Prior to LCD Display Various decisions related to hardware and software must be made before using the LCD controller/driver with an LCD display. The settings are described below. 1. * Hardware settings Use at 1/2 duty To use at 1/2 duty, connect pins V2 and V3 as shown in figure 13-2. VCC V1 V2 V3 VSS Figure 13-2 LCD Driver Power Supply Processing at 1/2 Duty * Large-panel display Because of the large impedance of the built-in resistive voltage divider, the H8/3834U Series LCD controller/driver is not well suited to driving large-panel displays. If use of a large panel leads to an unclear display, refer to 13.3.5 on boosting the LCD driver power supply. At static and 1/2 duty it is possible to boost the common output driving capacity. Set bit CMX to 1 when selecting the duty cycle. In this mode, at static duty pins COM4 to COM1 output the same waveform, while at 1/2 duty pins COM2 and COM1 output the COM1 waveform and pins COM4 and COM3 output the COM2 waveform. 346 * Segment expansion The HD66100 can be connected externally to expand the number of segments. See 13.3.3, Connection to HD66100. 2. * Software settings Duty cycle selection The duty cycle is selected in bits DTS1 and DTS0, with a choice of static, 1/2, 1/3, or 1/4 duty. * Segment driver selection The segment drivers to be used are selected in bits SGS3 to SGS0. * Frame frequency selection The frame frequency is selected in bits CKS3 to CKS0. The frame frequency should be selected depending on the specification of the LCD panel to be used. Refer to 13.3.4, Operation in PowerDown Modes, for information on clock selection in watch mode, subactive mode, and subsleep mode. 13.3.2 Relation of LCD RAM to Display The relation of the LCD RAM to segments depends on the duty cycle. LCD RAM memory maps for each duty cycle when segments are not expanded externally are shown in figures 13-3 to 13-6. When segments are expanded externally, the LCD RAM memory maps for each duty cycle are as shown in figures 13-7 to 13-10. It is also possible to use only external segments and not use the segment pins on this chip, in which case the LCD RAM memory map is as shown in figure 13-11. After setting the registers that control the LCD display, write data to the area corresponding to the duty cycle selected, using the same instructions as for the ordinary RAM. If the display is switched on, the data will be displayed automatically. Both word and byte access instructions can be used for writing to the LCD RAM. 347 13.3.3 Connection to HD66100 To expand the number of segments externally, connect the H8/3834U Series to the HD66100 segment chip. The HD66100 chip provides an additional 80 segments. When external segments are used, set bit SGX in LPCR for use of pins SEG40 to SEG37 as external segment expansion signal pins. Data will be output starting from LCD RAM pin SEG37. When bits SGS3 to SGS0 in LPCR are set to 0000, data will be output starting from LCD RAM pin SEG1. Figure 13-12 shows typical connections to the HD66100. The output level is determined by the combination of data pins and pin M; but that combination differs between the H8/3834U Series and the HD66100. Table 13-3 shows the output level of the LCD driver power supply. Figure 13-13 shows the common and segment waveforms at each duty. If bit ACT = 0, then if CL2 = 0, CL1 = 0 and M = 0, DO stops with the data output at that moment (1 or 0). In standby mode the expansion pins are in the high-impedance (floating) state. External expansion increases the load on the LCD panel, as a result of which the internal power supply may not have sufficient capacity. In that case refer to 13.3.5 on boosting the LCD driver power supply. Bit 7 H'F740 * SEG 2 Bit 6 SEG 2 Bit 5 SEG2 Bit 4 SEG 2 Bit 3 SEG 1 Bit 2 SEG 1 Bit 1 SEG 1 Bit 0 SEG 1 Internal driver display area H'F753 * SEG40 SEG40 SEG40 SEG40 SEG39 SEG39 SEG39 SEG39 Area not used for display H'F77F * COM 4 COM 3 COM 2 COM 1 COM 4 COM 3 COM 2 COM 1 Note: * Values immediately after reset. Figure 13-3 LCD RAM Map 1: No External Segment Expansion (1/4 Duty) 348 Bit 7 H'F740 * Bit 6 SEG 2 Bit 5 SEG 2 Bit 4 SEG 2 Bit 3 Bit 2 SEG 1 Bit 1 SEG 1 Bit 0 SEG 1 Internal driver display area H'F753 * SEG 40 SEG40 SEG40 SEG 39 SEG 39 SEG39 Area not used for display H'F77F * COM 3 COM 2 COM 1 COM 3 COM 2 COM 1 Note: * Values immediately after reset. Figure 13-4 LCD RAM Map 2: No External Segment Expansion (1/3 Duty) Bit 7 H'F740 * SEG 4 Bit 6 SEG 4 Bit 5 SEG 3 Bit 4 SEG 3 Bit 3 SEG 2 Bit 2 SEG 2 Bit 1 SEG 1 Bit 0 SEG 1 Internal driver display area H'F749 * SEG40 SEG 40 SEG 39 SEG39 SEG38 SEG38 SEG 37 SEG37 Area not used for display H'F77F * COM 2 COM 1 COM 2 COM 1 COM 2 COM 1 COM 2 COM 1 Note: * Values immediately after reset. Figure 13-5 LCD RAM Map 3: No External Segment Expansion (1/2 Duty) 349 Bit 7 H'F740 * H'F744 * SEG 8 SEG40 Bit 6 SEG 7 SEG39 Bit 5 SEG 6 SEG38 Bit 4 SEG 5 SEG37 Bit 3 SEG 4 SEG36 Bit 2 SEG 3 SEG35 Bit 1 SEG 2 SEG34 Bit 0 SEG 1 SEG33 Internal driver display area Area not used for display H'F77F * COM 1 COM 1 COM 1 COM 1 COM 1 COM 1 COM 1 COM 1 Note: * Values immediately after reset. Figure 13-6 LCD RAM Map 4: No External Segment Expansion (Static Duty) Bit 7 H'F740 * SEG2 Bit 6 SEG 2 Bit 5 SEG 2 Bit 4 SEG 2 Bit 3 SEG 1 Bit 2 SEG 1 Bit 1 SEG 1 Bit 0 SEG 1 Internal driver display area H'F751 * SEG 36 SEG 38 SEG 36 SEG 36 SEG 38 SEG 38 SEG 64 SEG 64 SEG 36 SEG 38 SEG 64 SEG 35 SEG 37 SEG 63 SEG 35 SEG 35 SEG 37 SEG 37 SEG 63 SEG 63 SEG 35 SEG 37 SEG 63 External driver display area (when CKS3 = CKS1 = CKS0 = 0) H'F75F * SEG 64 External driver display area H'F77F * SEG128 SEG 128 SEG 128 SEG128 SEG127 SEG 127 SEG 127 SEG127 COM4 COM 3 COM 2 COM 1 COM 4 COM 3 COM 2 COM 1 Note: * Values immediately after reset. Figure 13-7 LCD RAM Map 1: External Segment Expansion (1/4 Duty) 350 Bit 7 H'F740 * Bit 6 SEG 2 Bit 5 SEG 2 Bit 4 SEG 2 Bit 3 Bit 2 SEG1 Bit 1 SEG1 Bit 0 SEG1 Internal driver display area H'F751 * SEG 36 SEG 38 SEG 36 SEG 38 SEG 64 SEG 36 SEG 38 SEG 64 SEG 35 SEG 37 SEG 63 SEG 35 SEG 37 SEG 63 SEG 35 SEG 37 SEG 63 External driver display area (when CKS3 = CKS1 = CKS0 = 0) H'F75F * SEG 64 External driver display area H'F77F * SEG128 SEG128 SEG128 SEG127 SEG127 SEG127 COM 3 COM 2 COM 1 COM 3 COM 2 COM 1 Note: * Values immediately after reset. Figure 13-8 LCD RAM Map 2: External Segment Expansion (1/3 Duty) Bit 7 H'F740 * H'F748 * SEG4 SEG 36 SEG 40 Bit 6 SEG4 SEG 36 SEG 40 Bit 5 SEG3 SEG35 SEG39 Bit 4 SEG3 SEG35 SEG39 Bit 3 SEG2 SEG34 SEG38 Bit 2 SEG 2 SEG 34 SEG 38 Bit 1 SEG 1 SEG 33 SEG 37 Bit 0 SEG1 SEG 33 SEG 37 External driver display area (when CKS3 = CKS1 = CKS0 = 0) H'F75F * SEG128 SEG128 SEG127 SEG127 SEG126 SEG 126 SEG 125 SEG125 External driver display area Internal driver display area H'F77F * SEG256 SEG256 SEG255 SEG255 SEG254 SEG 254 SEG 253 SEG253 COM 2 COM 1 COM 2 COM 1 COM 2 COM 1 COM 2 COM 1 Note: * Values immediately after reset. Figure 13-9 LCD RAM Map 3: External Segment Expansion (1/2 Duty) 351 Bit 7 H'F740 * H'F744 * SEG 8 SEG40 Bit 6 Bit 5 Bit 4 SEG 5 SEG37 Bit 3 SEG 4 SEG 36 Bit 2 SEG 3 SEG 35 Bit 1 SEG 2 SEG 34 Bit 0 SEG 1 SEG33 Internal driver display area SEG 7 SEG 6 SEG 39 SEG 38 External driver display area (when CKS3 = CKS1 = CKS0 = 0) H'F75F * SEG 256 SEG 255 SEG 254 SEG 253 SEG 252 SEG 251 SEG 250 SEG 249 External driver display area H'F77F * SEG 512 SEG 511 SEG 510 SEG 509 SEG 508 SEG 507 SEG 506 SEG 505 COM 1 COM 1 COM 1 COM 1 COM 1 COM 1 COM 1 COM 1 Note: * Values immediately after reset. Figure 13-10 LCD RAM Map 4: External Segment Expansion (Static Duty) Bit 7 H'F740 * SEG2 Bit 6 SEG 2 Bit 5 SEG2 Bit 4 SEG2 Bit 3 SEG1 Bit 2 SEG1 Bit 1 SEG 1 Bit 0 SEG 1 External driver display area (when CKS3 = CKS1 = CKS0 = 0) H'F75F * SEG 64 SEG64 SEG 64 SEG 64 SEG 63 SEG 63 SEG 63 SEG 63 External driver display area H'F77F * SEG128 SEG128 SEG128 SEG128 SEG127 SEG127 SEG 127 SEG127 COM 4 COM 3 COM 2 COM 1 COM 4 COM 3 COM 2 COM 1 Note: * Values immediately after reset. Figure 13-11 LCD RAM Map When All External Segments are Used (Example: SGX = 1, SGS3 to SGS0 = 0000, 1/4 Duty) 352 1/3 bias; 1/4 duty or 1/3 duty VCC V1 V2 V3 This LSI VSS VCC V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M HD66100 SEG 40 /CL1 SEG 39 /CL2 SEG 38 /DO SEG 37 /M 1/2 duty VCC V1 V2 V3 This LSI VSS SEG 40 /CL1 SEG 39 /CL2 SEG 38 /DO SEG 37 /M Static VCC V1 V2 V3 This LSI VSS VCC V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M HD66100 SEG 40 /CL1 SEG 39 /CL2 SEG 38 /DO SEG 37 /M VCC V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M HD66100 Figure 13-12 Connection to HD66100 353 1 frame M Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM 1 COM 2 COM 3 COM 4 SEG n Figure 13-13 (a) Waveforms at 1/4 Duty 1 frame M Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM 1 COM 2 COM 3 SEG n V1 V2 V3 VSS Figure 13-13 (b) Waveforms at 1/3 Duty 354 1 frame M Data V1 V2 , V 3 VSS V1 V2 , V 3 VSS COM 1 COM 2 SEG n Figure 13-13 (c) Waveforms at 1/2 Duty 1 frame M Data V1 COM 1 VSS V1 SEG n VSS Figure 13-13 (d) Waveforms at Static Duty 355 Table 13-3 Output Levels Data M Static Common output Segment output 1/2 duty Common output Segment output 1/3 duty Common output Segment output 1/4 duty Common output Segment output 0 0 V1 V1 V2, V3 V1 V3 V2 V3 V2 0 1 VSS VSS V2, V3 VSS V2 V3 V2 V3 1 0 V1 VSS V1 VSS V1 VSS V1 VSS 1 1 VSS V1 VSS V1 VSS V1 VSS V1 13.3.4 Operation in Power-Down Modes The LCD controller/driver can be operated in the low-power modes, as shown in table 13-4. In the subactive, watch, and subsleep modes, the system clock pulse generator stops running, so no clock signal will be supplied and the display will be stopped, unless oW or oW/2 was selected when setting bits CKS3 to CKS0 in LCR. Since this may result in a direct current being applied to the LCD panel, be sure to select oW or oW/2 as the clock if these modes are used. In active (medium-speed) mode the system clock is changed, making it necessary to adjust the frame frequency setting (in bits CKS3 to CKS0) to avoid a change in frame frequency. Table 13-4 LCD Controller/Driver Operation in Power-Down Modes Mode Clock o oW Display Reset Active Sleep Watch Subactive Subsleep Stopped Running Stopped On*3 Standby Stopped Stopped*1 Stopped*2 Stopped*2 Running Running Running Stopped Stopped Running Running Running Running Running ACT = 0 Stopped Stopped Stopped Stopped Stopped ACT = 1 Stopped On On On*3 On*3 Notes: 1. The subclock pulse generator does not stop, but clock supply is stopped. 2. The LCD driver power supply resistive voltage divider is off regardless of bit PSW. 3. The display will not function unless oW or oW/2 is selected as the clock. 356 13.3.5 Boosting the LCD Driver Power Supply When a large LCD panel is driven, or if segments are expanded externally, the built-in power supply capacity may be insufficient, making it necessary to lower the power supply impedance. One method, shown in figure 13-12, is to connect a bypass capacitor of around 0.1 F to 0.3 F to pins V1, V2, and V3. Another approach, shown in figure 13-14 below, is to connect a resistive voltage divider externally. VCC V1 R R R = several k C = 0.1 F to 0.3 F This LSI V2 R V3 VSS R Figure 13-14 Connecting an External Resistive Voltage Divider 357 Section 14 Electrical Characteristics 14.1 H8/3834U Series Absolute Maximum Ratings Table 14-1 lists the absolute maximum ratings. Table 14-1 Absolute Maximum Ratings Item Power supply voltage Analog power supply voltage Programming voltage Input voltage Ports other than ports B and C Ports B and C Operating temperature Storage temperature Symbol VCC AVCC VPP Vin AVin Topr Tstg Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to +13.0 -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -20 to +75 -55 to +125 Unit V V V V V C C Note: Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 359 14.2 H8/3833U and H8/3834U Electrical Characteristics 14.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3833U and H8/3834U are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range of H8/3833U and H8/3834U 10.0 f OSC (MHz) 32.768 5.0 fw (kHz) 2.7 4.0 5.5 VCC (V) 2.0 2.7 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode * All operating modes 360 2. Power supply voltage vs. clock frequency range of H8/3833U and H8/3834U 5.0 oSUB (kHz) 2.7 4.0 5.5 VCC (V) 16.384 o (MHz) 2.5 8.192 4.096 0.5 2.7 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode (except CPU) * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) 625.0 500.0 o (kHz) 312.5 62.5 2.7 4.0 5.5 VCC (V) * Active mode (medium speed) 3. Analog power supply voltage vs. A/D converter operating range of H8/3833U and H8/3834U 5.0 o (MHz) 625.0 500.0 2.5 o (kHz) 2.7 4.0 AVCC * Active (high speed) mode * Sleep mode 5.5 (V) 312.5 0.5 62.5 2.7 4.0 5.5 AVCC (V) * Active (medium speed) mode 361 14.2.2 DC Characteristics Table 14-2 lists the DC characteristics of the H8/3833U and H8/3834U. Table 14-2 DC Characteristics of H8/3833U and H8/3834U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Input high voltage Symbol VIH Applicable Pins RES, MD0, WKP0 to WKP7, IRQ0 to IRQ4, TMIB, TMIC, TMIF CS, TMIG, SCK1, SCK2, SCK3, ADTRG UD, SI1, SI2, RXD OSC1 P10 to P17 P20 to P27 P30 to P37 P40 to P43 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 Input low voltage VIL RES, MD0, WKP0 to WKP7, IRQ0 to IRQ4, TMIB, TMIC, TMIF, CS, TMIG, SCK1, SCK2, SCK3, ADTRG UD, SI1, SI2, RXD OSC1 Note: Connect pin TEST to VSS. Min 0.8 VCC Typ -- Max VCC + 0.3 Unit V Test Condition VCC = 4.0 V to 5.5 V Note 0.9 VCC -- VCC + 0.3 0.7 VCC 0.8 VCC -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC - 0.5 -- VCC - 0.3 -- 0.7 VCC -- V V 0.8 VCC -- VCC + 0.3 0.7 VCC 0.8 VCC -0.3 -- -- -- AVCC + 0.3 V AVCC + 0.3 0.2 VCC V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V -0.3 -- 0.1 VCC -0.3 -0.3 -0.3 -0.3 -- -- -- -- 0.3 VCC 0.2 VCC 0.5 0.3 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V V 362 Table 14-2 DC Characteristics of H8/3833U and H8/3834U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Input low voltage Symbol VIL Applicable Pins P10 to P17 P20 to P27 P30 to P37 P40 to P43 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 P10 to P17 P20 to P27 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 P10 to P17 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 P20 to P27 P30 to P37 Min -0.3 Typ -- Max 0.3 VCC Unit V Test Condition VCC = 4.0 V to 5.5 V Note -0.3 -- 0.2 VCC Output VOH high voltage VCC - 1.0 -- -- V VCC = 4.0 V to 5.5 V -IOH = 1.0 mA VCC = 4.0 V to 5.5 V -IOH = 0.5 mA -IOH = 0.1 mA VCC - 0.5 -- -- VCC - 0.5 -- -- Output VOL low voltage -- -- -- -- -- -- 0.6 0.5 0.5 V VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA IOL = 0.4 mA -- -- -- -- -- -- 1.5 0.6 0.5 VCC = 4.0 V to 5.5 V IOL = 10 mA VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA Note: Connect pin TEST to VSS. 363 Table 14-2 DC Characteristics of H8/3833U and H8/3834U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Input leakage current Symbol |IIL| Applicable Pins RES, P43 OSC1, MD0 P10 to P17 P20 to P27 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 Pull-up MOS current -IP P10 to P17 P30 to P37 P50 to P57 P60 to P67 All input pins except power supply, RES, P43 pin RES Min -- -- -- Typ -- -- -- Max 20 1 1 A Unit A Test Condition VIN = 0.5 V to VCC - 0.5 V VIN = 0.5 V to VCC - 0.5 V Note 2 1 -- 50 -- -- -- -- 35 -- 1 300 -- 15 A A pF VIN = 0.5 V to AVCC - 0.5 V VCC = 5 V, VIN = 0 V VCC = 2.7 V, VIN = 0 V f = 1 MHz, VIN = 0 V Ta = 25C 2 1 2 1 Reference value Input CIN capacitance -- -- -- -- -- -- 60 15 30 15 P43 -- -- Notes: 1. Applies to HD6433833U and HD6433834U. 2. Applies to HD6473834U. 364 Table 14-2 DC Characteristics of H8/3833U and H8/3834U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Active mode current dissipation Symbol IOPE1 IOPE2 ISLEEP Applicable Pins VCC VCC VCC Min -- -- -- Typ Max Unit Test Condition 12 2.5 5 24 5 10 mA mA mA Active mode (high speed), VCC = 5 V, fosc = 10 MHz Note 1, 2 Active mode (medium speed), 1, 2 VCC = 5 V, fosc = 10 MHz VCC = 5 V, fosc = 10 MHz 1, 2 Sleep mode current dissipation Subactive mode ISUB current dissipation VCC -- 50 130 A VCC = 2.7 V, LCD on, 32-kHz crystal oscillator (oSUB = ow/2) VCC = 2.7 V, LCD on, 32-kHz crystal oscillator (oSUB = ow/8) VCC = 2.7 V, LCD on, 32-kHz crystal oscillator (oSUB = ow/2) VCC = 2.7 V, LCD not used, 32-kHz crystal oscillator (oSUB = ow/8) 32-kHz crystal oscillator not used 1, 2 -- 40 -- A Reference value 1, 2 1, 2 Subsleep mode current dissipation Watch mode current dissipation Standby mode current dissipation ISUBSP VCC -- 40 90 A IWATCH VCC -- -- 6 A 1, 2 ISTBY VCC -- -- 5 A 1, 2 RAM data VRAM retaining voltage VCC 2 -- -- V 1, 2 Notes: 1. Pin states during current measurement RES Pin Other Pins VCC LCD Power Supply Open Mode Internal State Operates Oscillator Pins System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC Active mode VCC (high and medium speed) Sleep mode Subactive mode Subsleep mode Watch mode Standby mode VCC VCC VCC VCC VCC Only timer operates Operates Only timer operates, CPU stops Only time-base clock operates, CPU stops CPU and timers all stop VCC VCC VCC VCC VCC Open Open Open Open Open System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC System clock oscillator: Crystal Subclock oscillator: Crystal 2. Excludes current in pull-up MOS transistors and output buffers. 365 Table 14-2 DC Characteristics of H8/3833U and H8/3834U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Allowable output low current (per pin) Symbol IOL Applicable Pins Output pins except in ports 2 and 3 Ports 2 and 3 All output pins Allowable output low current (total) IOL Output pins except in ports 2 and 3 Ports 2 and 3 All output pins Allowable output high current (per pin) Allowable output high current (total) -IOH -IOH All output pins Min -- -- -- -- -- -- -- -- All output pins -- -- Typ -- -- -- -- -- -- -- -- -- -- Max 2 10 0.5 40 80 20 2 0.2 15 10 mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Unit mA Test Condition VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V 366 14.2.3 AC Characteristics Table 14-3 lists the control signal timing, and tables 14-4 and 14-5 list the serial interface timing of the H8/3833U and H8/3834U. Table 14-3 Control Signal Timing of H8/3833U and H8/3834U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise specified. Item System clock oscillation frequency OSC clock (oOSC) cycle time System clock (o) cycle time Subclock oscillation frequency Symbol fOSC tOSC tcyc fW X1, X2 X1, X2 Applicable Pins Min Typ -- -- Max 10 5 1000 ns 1000 16 tOSC kHz s tW tcyc tsubcyc ms VCC = 4.0 V to 5.5 V 2 VCC = 4.0 V to 5.5 V 1 Figure 14-1 1 Unit MHz Test Condition VCC = 4.0 V to 5.5 V Reference Figure OSC1, OSC2 2 2 OSC1, OSC2 100 -- 200 -- 2 -- -- -- 2 2 OSC1, OSC2 -- -- X1, X2 OSC1 OSC1 -- 40 80 -- -- 2000 ns 32.768 -- 30.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 -- 40 60 2 -- -- -- -- 15 20 15 20 -- Watch clock cycle time tW Subclock (oSUB) cycle time Instruction cycle time Oscillation stabilization trc time (crystal oscillator) Oscillation stabilization trc time External clock high width External clock low width tCPH tCPL tsubcyc s ns VCC = 4.0 V to 5.5 V Figure 14-1 VCC = 4.0 V to 5.5 V Figure 14-1 VCC = 4.0 V to 5.5 V Figure 14-1 VCC = 4.0 V to 5.5 V Figure 14-1 Figure 14-2 40 80 -- -- ns External clock rise time tCPr External clock fall time tCPf tREL RES ns -- -- ns Pin RES low width 10 tcyc Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 367 Table 14-3 Control Signal Timing of H8/3833U and H8/3834U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise specified. Item Input pin high width Symbol tIH Applicable Pins Min Typ -- Max -- Unit tcyc tsubcyc Test Condition Reference Figure Figure 14-3 IRQ0 to IRQ4 2 WKP0 to WKP7 ADTRG TMIB, TMIC TMIF, TMIG IRQ0 to IRQ4 2 WKP0 to WKP7 ADTRG TMIB, TMIC TMIF, TMIG UD 4 Input pin low width tIL -- -- tcyc tsubcyc Figure 14-3 Pin UD minimum modulation width tUDH tUDL -- -- tcyc tsubcyc Figure 14-4 Table 14-4 Serial Interface (SCI1, SCI2) Timing of H8/3833U and H8/3834U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time Serial output data delay time Serial input data setup time Serial input data hold time CS setup time CS hold time Symbol tscyc tSCKH tSCKL tSCKr tSCKf tSOD tSIS tSIH tCSS tCSH Applicable Pins SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SO1, SO2 SI1, SI2 SI1, SI2 CS CS Min Typ 2 0.4 0.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 60 80 60 80 200 350 -- -- -- -- -- -- tcyc tcyc Figure 14-6 Figure 14-6 ns VCC = 4.0 V to 5.5 V Figure 14-5 ns VCC = 4.0 V to 5.5 V Figure 14-5 ns VCC = 4.0 V to 5.5 V Figure 14-5 ns VCC = 4.0 V to 5.5 V Figure 14-5 Unit tcyc tscyc tscyc ns Test Condition Reference Figure Figure 14-5 Figure 14-5 Figure 14-5 VCC = 4.0 V to 5.5 V Figure 14-5 200 -- 400 -- 200 -- 400 -- 2 2 -- -- 368 Table 14-5 Serial Interface (SCI3) Timing of H8/3833U and H8/3834U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Input clock cycle Asynchronous Synchronous Input clock pulse width Transmit data delay time (synchronous mode) Receive data setup time (synchronous mode) Receive data hold time (synchronous mode) tSCKW tTXD tRXS tRXH Symbol Min tscyc 4 6 0.4 -- -- 200 400 200 400 Typ -- -- -- -- -- -- -- -- -- Max -- -- 0.6 1 1 -- -- -- -- ns VCC = 4.0 V to 5.5 V Figure 14-8 ns VCC = 4.0 V to 5.5 V Figure 14-8 tscyc tcyc Figure 14-7 VCC = 4.0 V to 5.5 V Figure 14-8 Unit tcyc Test Condition Reference Figure Figure 14-7 369 14.2.4 A/D Converter Characteristics Table 14-6 shows the A/D converter characteristics of the H8/3833U and H8/3834U. Table 14-6 A/D Converter Characteristics of H8/3833U and H8/3834U VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Analog power supply voltage Analog input voltage Analog power supply current Symbol AVCC AVIN AIOPE AISTOP1 Applicable Pins AVCC AN0 to AN11 AVCC AVCC Min 2.7 -0.3 -- -- Typ Max -- -- -- 5.5 Unit Test Condition V Note 1 AVCC + 0.3 V 1.5 mA A AVCC = 5.0 V 2 Reference value 3 150 -- AISTOP2 Analog input capacitance CAIN AVCC AN0 to AN11 -- -- -- -- -- -- 5 30 10 A pF k Allowable signal RAIN source impedance Resolution (data length) Non-linearity error Quantization error Absolute accuracy Conversion time -- -- -- -- 12.4 24.8 -- -- -- -- -- -- 8 2.0 0.5 2.5 124 124 bit LSB LSB LSB s AVCC = 4.5 V to 5.5 V Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 370 14.2.5 LCD Characteristics Table 14-7 lists the LCD characteristics, and table 14-8 lists the AC characteristics for external segment expansion of the H8/3833U and H8/3834U. Table 14-7 LCD Characteristics of H8/3833U and H8/3834U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise specified. Item Segment driver voltage drop Common driver voltage drop LCD power supply voltage divider resistance LCD power supply voltage Symbol VDS VDC RLCD Applicable Pins SEG1 to SEG40 COM1 to COM4 Min -- -- 50 Typ -- -- 300 Max 0.6 0.3 900 Unit V V k Test Condition ID = 2 A ID = 2 A Between V1 and VSS 2 Note 1 1 VLCD V1 2.7 -- VCC V Notes: 1. These are the voltage drops between the voltage supply pins V1, V2, V3 , and Vss, and the segment pins or common pins. 2. When VLCD is supplied from an external source, the following relation must hold: VCC V1 V2 V3 VSS Table 14-8 AC Characteristics for External Segment Expansion of H8/3833U and H8/3834U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise specified. Item Clock high width Clock low width Clock setup time Data setup time Data hold time M delay time Clock rise and fall times Symbol tCWH tCWL tCSU tSU tDH tDM tCT Applicable Pins CL1, CL2 CL2 CL1, CL2 DO DO M CL1, CL2 Min 800 800 500 300 300 Typ -- -- -- -- -- Max -- -- -- -- -- Unit ns ns ns ns ns Test Condition * * * * * Reference Figure Figure 14-9 Figure 14-9 Figure 14-9 Figure 14-9 Figure 14-9 Figure 14-9 Figure 14-9 -1000 -- -- -- 1000 ns 100 ns Note: * Value when the frame frequency is set to between 30.5 Hz and 488 Hz. 371 14.3 H8/3835U, H8/3836U, and H8/3837U Electrical Characteristics 14.3.1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3835U, H8/3836U, and H8/3837U are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range of H8/3835U, H8/3836U, and H8/3837U 10.0 f OSC (MHz) 32.768 5.0 fw (kHz) 2.7 4.0 5.5 VCC (V) 2.0 2.7 4.0 5.5 VCC (V) * Active mode (high speeds) * Sleep mode * All operating modes 372 2. Power supply voltage vs. clock frequency range of H8/3835U, H8/3836U, and H8/3837U 5.0 oSUB (kHz) 2.7 4.0 5.5 VCC (V) 16.384 o (MHz) 2.5 8.192 4.096 0.5 2.7 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode (except CPU) * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) 625.0 500.0 o (kHz) 312.5 62.5 2.7 4.0 5.5 VCC (V) * Active mode (medium speed) 3. Analog power supply voltage vs. A/D converter operating range of H8/3835U, H8/3836U, and H8/3837U 5.0 o (MHz) 625.0 500.0 2.5 o (kHz) 2.7 4.0 5.5 AVCC (V) 312.5 0.5 62.5 2.7 4.0 5.5 AVCC (V) * Active (high speed) mode * Sleep mode * Active (medium speed) mode 373 14.3.2 DC Characteristics Table 14-9 lists the DC characteristics of the H8/3835U, H8/3836U, and H8/3837U. Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Input high voltage Symbol VIH Applicable Pins RES, MD0, WKP0 to WKP7, IRQ0 to IRQ4, TMIB, TMIC, TMIF CS, TMIG, SCK1, SCK2, SCK3, ADTRG UD, SI1, SI2, RXD OSC1 P10 to P17 P20 to P27 P30 to P37 P40 to P43 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 Input low voltage VIL RES, MD0, WKP0 to WKP7, IRQ0 to IRQ4, TMIB, TMIC, TMIF, CS, TMIG, SCK1, SCK2, SCK3, ADTRG UD, SI1, SI2, RXD OSC1 Note: Connect pin TEST to VSS. Min 0.8 VCC Typ -- Max VCC + 0.3 Unit V Test Condition VCC = 4.0 V to 5.5 V Note 0.9 VCC -- VCC + 0.3 0.7 VCC 0.8 VCC -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V VCC - 0.5 -- VCC - 0.3 -- 0.7 VCC -- V V 0.8 VCC -- VCC + 0.3 0.7 VCC 0.8 VCC -0.3 -- -- -- AVCC + 0.3 V AVCC + 0.3 0.2 VCC V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V -0.3 -- 0.1 VCC -0.3 -0.3 -0.3 -0.3 -- -- -- -- 0.3 VCC 0.2 VCC 0.5 0.3 V VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V V 374 Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Input low voltage Symbol VIL Applicable Pins P10 to P17 P20 to P27 P30 to P37 P40 to P43 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 P10 to P17 P20 to P27 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 P10 to P17 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 P20 to P27 P30 to P37 Min -0.3 Typ -- Max 0.3 VCC Unit V Test Condition VCC = 4.0 V to 5.5 V Note -0.3 -- 0.2 VCC Output VOH high voltage VCC - 1.0 -- -- V VCC = 4.0 V to 5.5 V -IOH = 1.0 mA VCC = 4.0 V to 5.5 V -IOH = 0.5 mA -IOH = 0.1 mA VCC - 0.5 -- -- VCC - 0.5 -- -- Output VOL low voltage -- -- -- -- -- -- 0.6 0.5 0.5 V VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA IOL = 0.4 mA -- -- -- -- -- -- 1.5 0.6 0.5 VCC = 4.0 V to 5.5 V IOL = 10 mA VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA Note: Connect pin TEST to VSS. 375 Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Input leakage current Symbol |IIL| Applicable Pins RES, P43 OSC1, MD0 P10 to P17 P20 to P27 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 Pull-up MOS current -IP P10 to P17 P30 to P37 P50 to P57 P60 to P67 All input pins except power supply, RES P43 pin RES Min -- -- -- Typ -- -- -- Max 20 1 1 A Unit A Test Condition VIN = 0.5 V to VCC - 0.5 V VIN = 0.5 V to VCC - 0.5 V Note 2 1 -- 50 -- -- -- -- 35 -- 1 300 -- 15 A A pF VIN = 0.5 V to AVCC - 0.5 V VCC = 5 V, VIN = 0 V VCC = 2.7 V, VIN = 0 V f = 1 MHz, VIN = 0 V Ta = 25C 2 1 2 1 Reference value Input CIN capacitance -- -- -- -- -- -- 60 15 30 15 P43 -- -- Notes: 1. Applies to HD6433835U, HD6433836U, and HD6433837U. 2. Applies to HD6473837U. 376 Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Active mode current dissipation Symbol IOPE1 IOPE2 ISLEEP Applicable Pins VCC VCC VCC Min -- -- -- Typ Max 13.5 24.0 2.5 5.0 5.0 10.0 Unit Test Condition mA mA mA Active mode (high speed), VCC = 5 V, fosc = 10 MHz Note 1, 2 Active mode (medium speed), 1, 2 VCC = 5 V, fosc = 10 MHz VCC = 5 V, fosc = 10 MHz 1, 2 Sleep mode current dissipation Subactive mode ISUB current dissipation VCC -- 50.0 130.0 A VCC = 2.7 V, LCD on, 32-kHz crystal oscillator (oSUB = ow/2) VCC = 2.7 V, LCD on, 32-kHz crystal oscillator (oSUB = ow/8) VCC = 2.7 V, LCD on, 32-kHz crystal oscillator (oSUB = ow/2) VCC = 2.7 V, LCD not used, 32-kHz crystal oscillator (oSUB = ow/8) 32-kHz crystal oscillator not used 1, 2 -- 40.0 -- A Reference value 1, 2 1, 2 Subsleep mode current dissipation Watch mode current dissipation Standby mode current dissipation ISUBSP VCC -- 40.0 90.0 A IWATCH VCC -- -- 6 A 1, 2 ISTBY VCC -- -- 5 A 1, 2 RAM data VRAM retaining voltage VCC 2 -- -- V 1, 2 Notes: 1. Pin states during current measurement RES Pin Other Pins VCC LCD Power Supply Open Mode Internal State Operates Oscillator Pins System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC Active mode VCC (high and medium speed) Sleep mode Subactive mode Subsleep mode Watch mode Standby mode VCC VCC VCC VCC VCC Only timer operates Operates Only timer operates, CPU stops Only time-base clock operates, CPU stops CPU and timers all stop VCC VCC VCC VCC VCC Open Open Open Open Open System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC System clock oscillator: Crystal Subclock oscillator: Crystal 2. Excludes current in pull-up MOS transistors and output buffers. 377 Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise indicated. Item Allowable output low current (per pin) Symbol IOL Applicable Pins Output pins except in ports 2 and 3 Ports 2 and 3 All output pins Allowable output low current (total) IOL Output pins except in ports 2 and 3 Ports 2 and 3 All output pins Allowable output high current (per pin) Allowable output high current (total) -IOH -IOH All output pins Min -- -- -- -- -- -- -- -- All output pins -- -- Typ -- -- -- -- -- -- -- -- -- -- Max 2 10 0.5 40 80 20 2 0.2 15 10 mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Unit mA Test Condition VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V 378 14.3.3 AC Characteristics Table 14-10 lists the control signal timing, and tables 14-11 and 14-12 list the serial interface timing of the H8/3835U, H8/3836U, and H8/3837U. Table 14-10 Control Signal Timing of H8/3835U, H8/3836U, and H8/3837U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise specified. Item System clock oscillation frequency OSC clock (oOSC) cycle time System clock (o) cycle time Subclock oscillation frequency Watch clock (oW) cycle time Subclock (oSUB) cycle time Instruction cycle time Oscillation stabilization trc time (crystal oscillator) Oscillation stabilization trc time External clock high width External clock low width tCPH tCPL Symbol fOSC tOSC tcyc fW tW tsubcyc X1, X2 X1, X2 Applicable Pins Min Typ -- -- Max 10 5 1000 ns 1000 16 tOSC kHz s tW tcyc tsubcyc ms VCC = 4.0 V to 5.5 V 2 VCC = 4.0 V to 5.5 V 1 Figure 14-1 1 Unit MHz Test Condition VCC = 4.0 V to 5.5 V Reference Figure OSC1, OSC2 2 2 OSC1, OSC2 100 -- 200 -- 2 -- -- -- 2 2 OSC1, OSC2 -- -- X1, X2 OSC1 OSC1 -- 40 80 40 80 -- -- -- -- 2000 ns 32.768 -- 30.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 -- 40 60 2 -- -- -- -- 15 20 15 20 -- s ns VCC = 4.0 V to 5.5 V Figure 14-1 VCC = 4.0 V to 5.5 V Figure 14-1 VCC = 4.0 V to 5.5 V Figure 14-1 VCC = 4.0 V to 5.5 V Figure 14-1 Figure 14-2 ns External clock rise time tCPr External clock fall time tCPf tREL RES ns -- -- ns Pin RES low width 10 tcyc Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 379 Table 14-10 Control Signal Timing of H8/3835U, H8/3836U, and H8/3837U (cont) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise specified. Item Input pin high width Symbol tIH Applicable Pins Min Typ -- Max -- Unit tcyc tsubcyc Test Condition Reference Figure Figure 14-3 IRQ0 to IRQ4 2 WKP0 to WKP7 ADTRG TMIB, TMIC TMIF, TMIG IRQ0 to IRQ4 2 WKP0 to WKP7 ADTRG TMIB, TMIC TMIF, TMIG UD 4 Input pin low width tIL -- -- tcyc tsubcyc Figure 14-3 Pin UD minimum modulation width tUDH tUDL -- -- tcyc tsubcyc Figure 14-4 Table 14-11 Serial Interface (SCI1, SCI2) Timing of H8/3835U, H8/3836U, and H8/3837U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time Serial output data delay time Serial input data setup time Serial input data hold time CS setup time CS hold time Symbol tscyc tSCKH tSCKL tSCKr tSCKf tSOD tSIS tSIH tCSS tCSH Applicable Pins SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SO1, SO2 SI1, SI2 SI1, SI2 CS CS Min Typ 2 0.4 0.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 60 80 60 80 200 350 -- -- -- -- -- -- tcyc tcyc Figure 14-6 Figure 14-6 ns VCC = 4.0 V to 5.5 V Figure 14-5 ns VCC = 4.0 V to 5.5 V Figure 14-5 ns VCC = 4.0 V to 5.5 V Figure 14-5 ns VCC = 4.0 V to 5.5 V Figure 14-5 Unit tcyc tscyc tscyc ns Test Condition Reference Figure Figure 14-5 Figure 14-5 Figure 14-5 VCC = 4.0 V to 5.5 V Figure 14-5 200 -- 400 -- 200 -- 400 -- 2 2 -- -- 380 Table 14-12 Serial Interface (SCI3) Timing of H8/3835U, H8/3836U, and H8/3837U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Input clock cycle Asynchronous Synchronous Input clock pulse width Transmit data delay time (synchronous mode) Receive data setup time (synchronous mode) Receive data hold time (synchronous mode) tSCKW tTXD tRXS tRXH Symbol Min tscyc 4 6 0.4 -- -- 200 400 200 400 Typ -- -- -- -- -- -- -- -- -- Max -- -- 0.6 1 1 -- -- -- -- ns VCC = 4.0 V to 5.5 V Figure 14-8 ns VCC = 4.0 V to 5.5 V Figure 14-8 tscyc tcyc Figure 14-7 VCC = 4.0 V to 5.5 V Figure 14-8 Unit tcyc Test Condition Reference Figure Figure 14-7 381 14.3.4 A/D Converter Characteristics Table 14-13 shows the A/D converter characteristics of the H8/3835U, H8/3836U, and H8/3837U. Table 14-13 A/D Converter Characteristics of H8/3835U, H8/3836U, and H8/3837U VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Analog power supply voltage Analog input voltage Analog power supply current Symbol AVCC AVIN AIOPE AISTOP1 Applicable Pins AVCC AN0 to AN11 AVCC AVCC Min 2.7 Typ Max -- 5.5 Unit Test Condition V Note 1 AVSS - 0.3 -- -- -- -- AVCC + 0.3 V 1.5 mA A AVCC = 5.0 V 2 Reference value 3 150 -- AISTOP2 Analog input capacitance CAIN AVCC AN0 to AN11 -- -- -- -- -- -- 5 30 10 A pF k Allowable signal RAIN source impedance Resolution (data length) Non-linearity error Quantization error Absolute accuracy Conversion time -- -- -- -- 12.4 24.8 -- -- -- -- -- -- 8 2.0 0.5 2.5 124 124 bit LSB LSB LSB s AVCC = 4.5 V to 5.5 V Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 382 14.3.5 LCD Characteristics Table 14-14 lists the LCD characteristics, and table 14-15 lists the AC characteristics for external segment expansion of the H8/3835U, H8/3836U, and H8/3837U. Table 14-14 LCD Characteristics of H8/3835U, H8/3836U, and H8/3837U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise specified. Item Segment driver voltage drop Common driver voltage drop LCD power supply voltage divider resistance LCD power supply voltage Symbol VDS VDC RLCD Applicable Pins SEG1 to SEG40 COM1 to COM4 Min -- -- 50 Typ -- -- 300 Max 0.6 0.3 900 Unit V V k Test Condition ID = 2 A ID = 2 A Between V1 and VSS 2 Note 1 1 VLCD V1 2.7 -- VCC V Notes: 1. These are the voltage drops between the voltage supply pins V1, V2, V3 , and Vss, and the segment pins or common pins. 2. When VLCD is supplied from an external source, the following relation must hold: VCC V1 V2 V3 VSS Table 14-15 AC Characteristics for External Segment Expansion of H8/3835U, H8/3836U, and H8/3837U VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, including subactive mode, unless otherwise specified. Item Clock high width Clock low width Clock setup time Data setup time Data hold time M delay time Clock rise and fall times Symbol tCWH tCWL tCSU tSU tDH tDM tCT Applicable Pins CL1, CL2 CL2 CL1, CL2 DO DO M CL1, CL2 Min 800 800 500 300 300 Typ -- -- -- -- -- Max -- -- -- -- -- Unit ns ns ns ns ns Test Condition * * * * * Reference Figure Figure 14-9 Figure 14-9 Figure 14-9 Figure 14-9 Figure 14-9 Figure 14-9 Figure 14-9 -1000 -- -- -- 1000 ns 100 ns Note: * Value when the frame frequency is set to between 30.5 Hz and 488 Hz. 383 14.4 Operation Timing Figures 14-1 to 14-10 show timing diagrams. t OSC VIH OSC 1 VIL t CPH t CPr t CPL t CPf Figure 14-1 System Clock Input Timing RES VIL tREL Figure 14-2 RES Low Width IRQ0 to IRQ 4 WKP0 to WKP7 ADTRG TMIB, TMIC TMIF, TMIG VIH VIL t IL t IH Figure 14-3 Input Timing 384 VIH UD VIL t UDL t UDH Figure 14-4 Minimum UD High and Low Width 385 t scyc SCK 1 SCK 2 V IH or V OH* V IL or V OL * t SCKL t SCKf t SOD t SCKH t SCKr SO 1 SO 2 VOH* VOL * t SIS t SIH SI 1 SI 2 Notes: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL = 0.8 V Load conditions are shown in figure 14-10. Figure 14-5 Serial Interface 1 and 2 Input/Output Timing 386 V IH CS V IL t CSS t CSH V IH SCK 2 V IL Figure 14-6 Serial Interface 2 Chip Select Timing t SCKW SCK 3 t scyc Figure 14-7 SCK3 Input Clock Timing 387 t scyc V IH or V OH* V IL or V OL * t TXD TXD (transmit data) VOH* VOL * t RXS TXD (receive data) Notes: * Output timing reference levels Output high: VOH= 2.0 V Output low: VOL = 0.8 V Load conditions are shown in figure 14-10. t RXH SCK 3 Figure 14-8 Input/Output Timing of Serial Interface 3 in Synchronous Mode t CT CL 1 t CWH t CSU VCC - 0.5 V CL 2 t CSU 0.4 V t CWL t CT DO t SU VCC - 0.5 V 0.4 V t DH VCC - 0.5 V 0.4 V t CWH M t DM 0.4 V Figure 14-9 Segment Expansion Signal Timing 388 14.5 Output Load Circuit VCC 2.4 k Output pin 30 pF 12 k Figure 14-10 Output Load Condition 389 Appendix A CPU Instruction Set A.1 Instructions Operation Notation Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx: 3/8/16 d: 8/16 @aa: 8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement Condition Code Notation Symbol * 0 -- Modified according to the instruction result Not fixed (value not guaranteed) Always cleared to 0 Not affected by the instruction execution result 391 Table A-1 lists the H8/300L CPU instruction set. Table A-1 Instruction Set Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd Operation @Rn Condition Code IHNZVC ---- ---- B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd W Rs16 Rd16 W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP W SP-2 SP Rs16 @SP Rn 2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2 0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6 0--6 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd PUSH Rs 392 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic EEPMOV Operation @Rn Condition Code I HNZVC Rn -- if R4L0 then Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next; B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8 -C Rd8 B Rd8-Rs8 -C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd Rd B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 ------------ ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd -- -- -- -- 2 2 2 2 2 -- ------------ 2 ------------ 2 ---- --* -- -- -- --2 *2 2 2 2 2 -- ------------ 2 ------------ 2 ---- --* -- -- -- --2 *--2 2 2 2 2 -- 393 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic MULXU.B Rs, Rd DIVXU.B Rs, Rd Operation @Rn Condition Code I HNZVC B Rd8 x Rs8 Rd16 B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd B C b7 b0 C b7 b0 0 b7 b0 C b7 b0 0 2 2 2 Rn 2 2 -- -- -- -- -- -- 14 -- -- -- -- 14 AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd ---- 2 ---- ---- 2 ---- ---- 2 2 2 ---- ---- ---- 0--2 0--2 0--2 0--2 0--2 0--2 0--2 2 SHAR.B Rd B 2 ---- 02 SHLL.B Rd B C 2 ---- 02 SHLR.B Rd B 0 2 ---- 0 0 2 ROTXL.B Rd B C b7 b0 2 ---- 02 ROTXR.B Rd B b7 b0 C 2 ---- 02 394 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic ROTL.B Rd Operation C b7 b0 @Rn Condition Code I HNZVC ---- Rn B 2 02 ROTR.B Rd B C b7 b0 2 ---- 02 BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 395 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd Operation @Rn Condition Code I HNZVC B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C Rn 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 ------ ---- 2 ------ ---- 6 ------ ---- 6 ------ ---- 2 ------ ---- 6 ------ ---- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 396 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8 Operation Branching Condition @Rn Condition Code I HNZVC B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If condition -- is true -- then -- PC PC+d:8 -- else next; -- -- -- -- -- -- -- -- -- -- PC Rn16 -- PC aa:16 -- PC @aa:8 -- SP-2 SP PC @SP PC PC+d:8 CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 2 2 4 2 4 Rn 4 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 4 4 4 2 2 ------------ 6 ------------ 8 ------------ 6 397 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic JSR @Rn Operation @Rn Condition Code I HNZVC -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 2 2 2 2 2 2 Rn 2 ------------ 6 JSR @aa:16 4 ------------ 8 JSR @@aa:8 2 ------------ 8 RTS RTE 2 ------------ 8 2 10 SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP 2 ------------ 2 2 2 2 2 2 ------------ 2 2 ------------ 2 Notes: * The number of execution states given here assumes the opcode and operand data are in on-chip memory. For other cases see Appendix A.3 below. Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. The number of states required for execution is 4n + 9 (n = value of R4L). Set to 1 if the divisor is negative; otherwise cleared to 0. Set to 1 if the divisor is zero; otherwise cleared to 0. 398 A.2 Operation Code Map Table A-2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 399 Table A-2 Operation Code Map 8 ADD SUB DEC SUBS CMP INC ADDS MOV 9 A B C D E ADDX SUBX Low High 0 1 2 3 4 5 6 7 F DAA DAS 0 NOP SLEEP STC LDC ORC XORC ANDC LDC SHLL SHLR ROTXL ROTXR NOT 1 OR XOR AND SHAL SHAR ROTL ROTR NEG 2 MOV 3 BVS JMP BPL BMI 4 BRA BRN BHI BLS BCC BCS BNE BEQ BVC BGE BLT BGT JSR MOV * BLE 5 MULXU DIVXU RTS BSR RTE BST 6 MOV BSET BNOT BCLR BTST BOR BXOR BAND BIST BLD EEPMOV Bit-manipulation instructions BIOR BIXOR BIAND BILD ADD ADDX CMP SUBX OR XOR AND MOV 400 7 8 9 A B C D E F Note: * The PUSH and POP instructions are identical in machine language to MOV instructions. A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A-4: I = L = 2, J = K = M = N= 0 From table A-3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A-4: I = 2, J = K = 1, L = M = N = 0 From table A-3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8 401 Table A-3 Number of Cycles in Each Instruction Execution Status (instruction cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation SI SJ SK SL SM SN 1 2 or 3* -- Access Location On-Chip Memory 2 On-Chip Peripheral Module -- Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for details. 402 Table A-4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 1 1 1 1 1 2 1 1 Word Data Internal Access Operation M N Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 2 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 2 BCLR #xx:3, @aa:8 2 BCLR Rn, Rd 1 403 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 1 2 1 1 2 2 Word Data Internal Access Operation M N Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 1 1 BIXOR #xx:3, @aa:8 2 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd 1 2 2 1 2 1 1 2 2 BNOT #xx:3, @aa:8 2 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd 1 2 2 1 2 2 1 2 2 2 1 1 2 2 BSET #xx:3, @aa:8 2 BSET Rn, Rd BSET Rn, @Rd 1 2 2 404 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 1 1 2 2 1 2 Word Data Internal Access Operation M N Instruction Mnemonic BSET BSR BST BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 2 CMP CMP. B #xx:8, Rd CMP. B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 12 2n+2* 1 2 2 2 1 Note: n: Initial value in R4L. The source and destination operands are accessed n + 1 times each. 405 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 2 1 1 2 1 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 12 2 2 1 1 1 1 1 1 1 1 1 2 2 Instruction Mnemonic MOV MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd MOV.W @(d:16, Rs), Rd 2 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd 1 2 1 MOV.W Rs, @(d:16, Rd) 2 MOV.W Rs, @-Rd MOV.W Rs, @aa:16 MULXU NEG NOP NOT OR MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC POP PUSH ROTL ROTR ROTXL ROTXR RTE RTS ORC #xx:8, CCR POP Rd PUSH Rs ROTL.B Rd ROTR.B Rd ROTXL.B Rd ROTXR.B Rd RTE RTS 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 2 2 2 2 406 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Word Data Internal Access Operation M N Instruction Mnemonic SHLL SHAL SHAR SHLR SLEEP STC SUB SHLL.B Rd SHAL.B Rd SHAR.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR 407 Appendix B On-Chip Registers B.1 I/O Registers (1) Address Register (low) Name Bit 7 H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 H'B9 H'BA TMA TCA TMB TMA7 TCA7 TMB7 TMA6 TCA6 -- TCB6/ TLB6 TMC6 TCC6/ TLC6 CKSH2 CMFH TCFH6 TCFL6 TMA5 TCA5 -- TCB5/ TLB5 TMC5 TCC5/ TLC5 CKSH1 OVIEH TCFH5 TCFL5 -- TCA4 -- TCB4/ TLB4 -- TCC4/ TLC4 CKSH0 CCLRH TCFH4 TCFL4 TMA3 TCA3 -- TCB3/ TLB3 -- TCC3/ TLC3 TOLL OVFL TCFH3 TCFL3 TMA2 TCA2 TMB2 TCB2/ TLB2 TMC2 TCC2/ TLC2 CKSL2 CMFL TCFH2 TCFL2 TMA1 TCA1 TMB1 TCB1/ TLB1 TMC1 TCC1/ TLC1 CKSL1 OVIEL TCFH1 TCFL1 TMA0 TCA0 TMB0 TCB0/ TLB0 TMC0 TCC0/ TLC0 CKSL0 CCLRL TCFH0 TCFL0 Timer F Timer C Timer B Timer A SCR1 SCSR1 SDRU SDRL STAR EDAR SCR2 SCSR2 SMR BRR SCR3 TDR SSR RDR SNC1 -- SDRU7 SDRL7 -- -- -- -- COM BRR7 TIE TDR7 TDRE RDR7 Bit Names Bit 6 SNC0 SOL SDRU6 SDRL6 -- -- -- -- CHR BRR6 RIE TDR6 RDRF RDR6 Bit 5 -- ORER SDRU5 SDRL5 -- -- -- -- PE BRR5 TE TDR5 OER RDR5 Bit 4 -- -- SDRU4 SDRL4 STA4 EDA4 GAP1 SOL PM BRR4 RE TDR4 FER RDR4 Bit 3 CKS3 -- SDRU3 SDRL3 STA3 EDA3 GAP0 ORER STOP BRR3 MPIE TDR3 PER RDR3 Bit 2 CKS2 -- SDRU2 SDRL2 STA2 EDA2 CKS2 WT MP BRR2 TEIE TDR2 TEND RDR2 Bit 1 CKS1 -- SDRU1 SDRL1 STA1 EDA1 CKS1 ABT CKS1 BRR1 CKE1 TDR1 MPBR RDR1 Bit 0 CKS0 STF SDRU0 SDRL0 STA0 EDA0 CKS0 STF CKS0 BRR0 CKE0 TDR0 MPBT RDR0 SCI3 SCI2 Module Name SCI1 TCB/TLB TCB7/ TLB7 TMC TMC7 TCC/TLC TCC7/ TLC7 TCRF TCSRF TCFH TCFL OCRFH TOLH OVFH TCFH7 TCFL7 OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 Notation: SCI1: Serial communication interface 1 SCI2: Serial communication interface 2 SCI3: Serial communication interface 3 408 Address Register (low) Name Bit 7 H'BB H'BC H'BD H'BE H'BF H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 H'D8 H'D9 H'DA H'DB H'DC H'DD PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA P17 P27 P37 -- P57 P67 P77 P87 P97 -- RLCTR PWCR -- -- PMR1 PMR2 PMR3 PMR4 PMR5 IRQ3 -- CS NMOD7 WKP7 AMR ADRR ADSR CKS ADR7 ADSF LPCR LCR DTS1 -- OCRFL TMG ICRGF ICRGR Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Timer F OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 DTS0 PSW CMX ACT SGX DISP SGS3 CKS3 SGS2 CKS2 SGS1 CKS1 SGS0 CKS0 LCD controller/ driver TRGE ADR6 -- -- ADR5 -- -- ADR4 -- CH3 ADR3 -- CH2 ADR2 -- CH1 ADR1 -- CH0 ADR0 -- A/D converter IRQ2 -- STRB NMOD6 WKP6 IRQ1 POF2 SO2 NMOD5 WKP5 PWM NCS SI2 NMOD4 WKP4 TMIG IRQ0 SCK2 NMOD3 WKP3 TMOFH POF1 SO1 NMOD2 WKP2 TMOFL UD SI1 NMOD1 WKP1 TMOW IRQ4 SCK1 NMOD0 WKP0 I/O ports -- -- -- -- -- -- -- -- RLCT1 RLCT0 PWDRU -- PWDRL -- -- -- -- PWCR0 14-bit PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWM PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 P16 P26 P36 -- P56 P66 P76 P86 P96 -- P15 P25 P35 -- P55 P65 P75 P85 P95 -- P14 P24 P34 -- P54 P64 P74 P84 P94 -- P13 P23 P33 P43 P53 P63 P73 P83 P93 PA3 P12 P22 P32 P42 P52 P62 P72 P82 P92 PA2 P11 P21 P31 P41 P51 P61 P71 P81 P91 PA1 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0 I/O ports 409 Address Register (low) Name Bit 7 H'DE H'DF H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF H'FF IWPR IWPF7 IRR1 IRR2 IRRTA IRRDT SYSCR1 SSBY SYSCR2 -- IEGR IENR1 IENR2 -- IENTA IENDT PDRB PDRC PUCR1 PUCR3 PUCR5 PUCR6 PCR1 PCR2 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA PB7 -- Bit Names Bit 6 PB6 -- Bit 5 PB5 -- Bit 4 PB4 -- Bit 3 PB3 PC3 Bit 2 PB2 PC2 Bit 1 PB1 PC1 Bit 0 PB0 PC0 Module Name I/O ports PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 PCR17 PCR27 PCR37 -- PCR57 PCR67 PCR77 PCR87 PCR97 -- PCR16 PCR26 PCR36 -- PCR56 PCR66 PCR76 PCR86 PCR96 -- PCR15 PCR25 PCR35 -- PCR55 PCR65 PCR75 PCR85 PCR95 -- PCR14 PCR24 PCR34 -- PCR54 PCR64 PCR74 PCR84 PCR94 -- PCR13 PCR23 PCR33 -- PCR53 PCR63 PCR73 PCR83 PCR93 PCRA3 PCR12 PCR22 PCR32 PCR42 PCR52 PCR62 PCR72 PCR82 PCR92 PCRA2 PCR11 PCR21 PCR31 PCR41 PCR51 PCR61 PCR71 PCR81 PCR91 PCRA1 PCR10 PCR20 PCR30 PCR40 PCR50 PCR60 PCR70 PCR80 PCR90 PCRA0 STS2 -- -- IENS1 IENAD STS1 -- -- IENWP IENS2 STS0 NESEL IEG4 IEN4 IENTG LSON DTON IEG3 IEN3 IENTFH -- MSON IEG2 IEN2 IENTFL -- SA1 IEG1 IEN1 IENTC -- SA0 IEG0 IEN0 IENTB System control IRRS1 IRRAD -- IRRS2 IRRI4 IRRTG IRRI3 IRRI2 IRRI1 IRRTC IRRI0 IRRTB IRRTFH IRRTFL System control IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 System control 410 B.2 I/O Registers (2) Register acronym Register name Address to which the register is mapped Name of on-chip supporting module Timer C TMC--Timer mode register C H'B4 Bit numbers Bit 7 TMC7 Initial value Read/Write 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W Initial bit values Names of the bits. Dashes (--) indicate reserved bits. Possible types of access R W Read only Write only R/W Read and write Clock select 0 0 0 Internal clock: o/8192 1 Internal clock: o/2048 1 0 Internal clock: o/512 1 Internal clock: o/64 1 0 0 Internal clock: o/16 1 Internal clock: o/4 1 0 Internal clock: o W /4 1 External event (TMIC): Rising or falling edge Counter up/down control 0 0 TCC is an up-counter 1 TCC is a down-counter 1 * TCC up/down control is determined by input at pin UD. TCC is a down-counter if the UD input is high, and an up-counter if the UD input is low. Full name of bit Descriptions of bit settings 411 SCR1--Serial control register 1 Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 CKS3 0 R/W H'A0 2 CKS2 0 R/W 1 CKS1 0 R/W SCI1 0 CKS0 0 R/W Clock Select (CKS2 to CKS0) Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Serial Clock Cycle Synchronous Prescaler Division o = 5 MHz o = 2.5 MHz o/1024 204.8 s 409.6 s o/256 51.2 s 102.4 s 12.8 s 25.6 s o/64 6.4 s 12.8 s o/32 3.2 s 6.4 s o/16 1.6 s 3.2 s o/8 0.8 s 1.6 s o/4 -- 0.8 s o/2 Clock source select 0 Clock source is prescaler S, and pin SCK 1 is output pin 1 Clock source is external clock, and pin SCK 1 is input pin Operation mode select 0 0 8-bit synchronous transfer mode 1 16-bit synchronous transfer mode 1 0 Continuous clock output mode 1 Reserved 412 SCSR1--Serial control/status register 1 Bit Initial value Read/Write 7 -- 1 -- 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 -- 0 -- 3 -- 0 -- H'A1 2 -- 0 -- 1 -- 0 -- 0 SCI1 STF 0 R/W Start flag 0 Read Write 1 Read Write Indicates that transfer is stopped Invalid Indicates transfer in progress Starts a transfer operation Overrun error flag 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] Set if a clock pulse is input after transfer is complete, when an external clock is used Extended data bit 0 Read SO 1 pin output level is low Write SO 1 pin output level changes to low 1 Read SO 1 pin output level is high Write SO 1 pin output level changes to high Note: * Only a write of 0 for flag clearing is possible. 413 SDRU--Serial data register U Bit Initial value Read/Write 7 SDRU7 R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 H'A2 2 SDRU2 R/W 1 SDRU1 R/W SCI1 0 SDRU0 R/W SDRU3 R/W Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Stores transmit and receive data 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data SDRL--Serial data register L Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 H'A3 2 SDRL2 R/W 1 SDRL1 R/W SCI1 0 SDRL0 R/W SDRL3 R/W Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Stores transmit and receive data 8-bit transfer mode: 8-bit data 16-bit transfer mode: Lower 8 bits of data STAR--Start address register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 STA4 0 R/W 3 STA3 0 R/W H'A4 2 STA2 0 R/W 1 STA1 0 R/W SCI2 0 STA0 0 R/W Transfer start address in range from H'FF80 to H'FF9F 414 EDAR--End address register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 EDA4 0 R/W 3 EDA3 0 R/W H'A5 2 EDA2 0 R/W 1 EDA1 0 R/W SCI2 0 EDA0 0 R/W Transfer end address in range from H'FF80 to H'FF9F SCR2--Serial control register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 GAP1 0 R/W 3 GAP0 0 R/W H'A6 2 CKS2 0 R/W 1 CKS1 0 R/W SCI2 0 CKS0 0 R/W Clock Select (CKS2 to CKS0) Bit 2 Bit 1 Bit 0 Clock Source CKS2 CKS1 CKS0 Pin SCK 2 0 0 0 SCK 2 output Prescaler S 1 1 0 1 1 0 0 1 1 0 External clock 1 SCK 2 input Prescaler Division o/256 o/64 o/32 o/16 o/8 o/4 o/2 -- Serial Clock Cycle o = 2.5 MHz o = 5 MHz 51.2 s 102.4 s 12.8 s 25.6 s 6.4 s 12.8 s 3.2 s 6.4 s 1.6 s 3.2 s 0.8 s 1.6 s -- 0.8 s -- -- Gap select 0 0 No gaps between bytes 1 A gap of 8 clock cycles is inserted between bytes 1 0 A gap of 24 clock cycles is inserted between bytes 1 A gap of 56 clock cycles is inserted between bytes 415 SCSR2--Serial control/status register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 SOL 0 R/W 3 ORER 0 H'A7 2 WT 0 R/(W)* 1 ABT 0 R/(W)* SCI2 0 STF 0 R/W R/(W)* Start flag 0 Read Write 1 Read Write Indicates that transfer is stopped Stops a transfer operation Indicates transfer in progress or waiting for CS input Starts a transfer operation Abort flag 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] When CS goes high during a transfer Wait flag 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] An attempt was made to read or write the (32-byte) serial data buffer during a transfer or while waiting for CS input Overrun error flag 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] Set if a clock pulse is input after transfer is complete, when an external clock is used Extended data bit 0 Read SO 2 pin output level is low Write SO 2 pin output level changes to low 1 Read SO 2 pin output level is high Write SO 2 pin output level changes to high Note: * Only a write of 0 for flag clearing is possible. 416 SMR--Serial mode register Bit Initial value Read/Write 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 H'A8 2 MP 0 R/W 1 CKS1 0 R/W SCI3 0 CKS0 0 R/W STOP 0 R/W Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit adding and checking disabled 1 Parity bit adding and checking enabled Character length 0 8-bit data 1 7-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode Clock select 0, 1 0 0 o clock 1 o/4 clock 1 0 o/16 clock 1 o/64 clock BRR--Bit rate register Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W H'A9 2 BRR2 1 R/W 1 BRR1 1 R/W SCI3 0 BRR0 1 R/W 417 SCR3--Serial control register 3 Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'AA 2 TEIE 0 R/W 1 CKE1 0 R/W SCI3 0 CKE0 0 R/W Clock enable Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 Transmit end interrupt enable 0 1 Transmit end interrupt (TEI) disabled Transmit end interrupt (TEI) enabled Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Description Clock Source Internal clock Internal clock Internal clock Reserved External clock External clock Reserved Reserved SCK 3 Pin Function I/O port Serial clock output Clock output Reserved Clock input Serial clock input Reserved Reserved Multiprocessor interrupt enable 0 Multiprocessor interrupt request disabled (ordinary receive operation) [Clearing condition] Multiprocessor bit receives a data value of 1 Multiprocessor interrupt request enabled Until a multiprocessor bit value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are disabled, and serial status register (SSR) flags RDRF, FER, and OER are not set. 1 Receive enable 0 1 Receive operation disabled (RXD is a general I/O port) Receive operation enabled (RXD is the receive data pin) Transmit enable 0 1 Transmit operation disabled (TXD is a general I/O port) Transmit operation enabled (TXD is the transmit data pin) Receive interrupt enable 0 1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Transmit interrupt enable (TIE) 0 1 Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled 418 TDR--Transmit data register Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W H'AB 2 TDR2 1 R/W 1 TDR1 1 R/W SCI3 0 TDR0 1 R/W Data to be transferred to TSR 419 SSR--Serial status register Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 OER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* H'AC 2 TEND 1 R 1 MPBR 0 R 0 SCI3 MPBT 0 R/W Multiprocessor bit receive 0 Indicates reception of data in which the multiprocessor bit is 0 1 Indicates reception of data in which the multiprocessor bit is 1 Multiprocessor bit transmit 0 The multiprocessor bit in transmit data is 0 1 The multiprocessor bit in transmit data is 1 Transmit end 0 Indicates that transmission is in progress [Clearing conditions] After reading TDRE = 1, cleared by writing 0 to TDRE. When data is written to TDR by an instruction. 1 Indicates that a transmission has ended [Setting conditions] When bit TE in serial control register 3 (SCR3) is 0. If TDRE is set to 1 when the last bit of a transmitted character is sent. Parity error 0 Indicates that data receiving is in progress or has been completed [Clearing conditions] After reading PER = 1, cleared by writing 0 1 Indicates that a parity error occurred in data receiving [Setting conditions] When the sum of 1s in received data plus the parity bit does not match the parity mode bit (PM) setting in the serial mode register (SMR) Framing error 0 Indicates that data receiving is in progress or has been completed [Clearing conditions] After reading FER = 1, cleared by writing 0 1 Indicates that a framing error occurred in data receiving [Setting conditions] The stop bit at the end of receive data is checked and found to be 0 Overrun error 0 Indicates that data receiving is in progress or has been completed [Clearing conditions] After reading OER = 1, cleared by writing 0 1 Indicates that an overrun error occurred in data receiving [Setting conditions] When data receiving is completed while RDRF is set to 1 Receive data register full 0 Indicates there is no receive data in RDR [Clearing conditions] After reading RDRF = 1, cleared by writing 0. When data is read from RDR by an instruction. 1 Indicates that there is receive data in RDR [Setting conditions] When receiving ends normally, with receive data transferred from RSR to RDR Transmit data register empty 0 Indicates that transmit data written to TDR has not been transferred to TSR [Clearing conditions] After reading TDRE = 1, cleared by writing 0. When data is written to TDR by an instruction. 1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR [Setting conditions] When bit TE in serial control register 3 (SCR3) is 0. When data is transferred from TDR to TSR. Note: * Only a write of 0 for flag clearing is possible. 420 RDR--Receive data register Bit Initial value Read/Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R H'AD 2 RDR2 0 R 1 RDR1 0 R SCI3 0 RDR0 0 R TMA--Timer mode register A Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 H'B0 2 TMA2 0 R/W 1 TMA1 0 R/W Timer A 0 TMA0 0 R/W TMA3 0 R/W Clock output select 0 0 0 o/32 1 o/16 1 0 o/8 1 o/4 1 0 0 o W /32 1 o W /16 1 0 o W /8 1 o W /4 Internal clock select Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period 0 0 0 o/8192 0 PSS 1 PSS o/4096 PSS o/2048 1 0 o/512 PSS 1 1 0 0 o/256 PSS 1 o/128 PSS o/32 1 0 PSS o/8 1 PSS 0 0 0 1s 1 PSW 1 0.5 s PSW 1 0 0.25 s PSW 1 0.03125 s PSW 1 0 0 PSW and TCA are reset 1 1 0 1 Function Interval timer Time base 421 TCA--Timer counter A Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R H'B1 2 TCA2 0 R 1 TCA1 0 R Timer A 0 TCA0 0 R Count value TMB--Timer mode register B Bit Initial value Read/Write 7 TMB7 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'B2 2 TMB2 0 R/W 1 TMB1 0 R/W Timer B 0 TMB0 0 R/W Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected Clock select 0 0 0 Internal clock: o/8192 1 Internal clock: o/2048 1 0 Internal clock: o/512 1 Internal clock: o/256 1 0 0 Internal clock: o/64 1 Internal clock: o/16 1 0 Internal clock: o/4 1 External event (TMIB): Rising or falling edge 422 TCB--Timer counter B Bit Initial value Read/Write 7 TCB7 0 R 6 TCB6 0 R 5 TCB5 0 R 4 TCB4 0 R 3 TCB3 0 R H'B3 2 TCB2 0 R 1 TCB1 0 R Timer B 0 TCB0 0 R Count value TLB--Timer load register B Bit Initial value Read/Write 7 TLB7 0 W 6 TLB6 0 W 5 TLB5 0 W 4 TLB4 0 W 3 TLB3 0 W H'B3 2 TLB2 0 W 1 TLB1 0 W Timer B 0 TLB0 0 W Reload value 423 TMC--Timer mode register C Bit Initial value Read/Write 7 TMC7 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- H'B4 2 TMC2 0 R/W 1 TMC1 0 R/W Timer C 0 TMC0 0 R/W Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected Clock select 0 0 0 Internal clock: o/8192 1 Internal clock: o/2048 1 0 Internal clock: o/512 1 Internal clock: o/64 1 0 0 Internal clock: o/16 1 Internal clock: o/4 1 0 Internal clock: o W /4 1 External event (TMIC): Rising or falling edge Counter up/down control 0 0 TCC is an up-counter 1 TCC is a down-counter 1 * TCC up/down control is determined by input at pin UD. TCC is a down-counter if the UD input is high, and an up-counter if the UD input is low. Note: * Don't care TCC--Timer counter C Bit Initial value Read/Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R H'B5 2 TCC2 0 R 1 TCC1 0 R Timer C 0 TCC0 0 R Count value 424 TLC--Timer load register C Bit Initial value Read/Write 7 TLC7 0 W 6 TLC6 0 W 5 TLC5 0 W 4 TLC4 0 W 3 TLC3 0 W H'B5 2 TLC2 0 W 1 TLC1 0 W Timer C 0 TLC0 0 W Reload value TCRF--Timer control register F H'B6 Timer F Bit Initial value Read/Write 7 TOLH 0 W 6 CKSH2 0 W 5 CKSH1 0 W 4 CKSH0 0 W 3 TOLL 0 W 2 CKSL2 0 W 1 CKSL1 0 W 0 CKSL0 0 W Toggle output level H 0 Low level 1 High level Clock select L 0 * * External event (TMIF): Rising or falling edge 1 0 0 Internal clock: o/32 1 Internal clock: o/16 1 0 Internal clock: o/4 1 Internal clock: o/2 Toggle output level L 0 Low level 1 High level Clock select H 0 * * 16-bit mode selected. TCFL overflow signals are counted. 1 0 0 Internal clock: o/32 1 Internal clock: o/16 1 0 Internal clock: o/4 1 Internal clock: o/2 Note: * Don't care 425 TCSRF--Timer control/status register F Bit Initial value Read/Write 7 OVFH 0 R/(W)* 6 CMFH 0 R/(W)* 5 OVIEH 0 R/W 4 CCLRH 0 R/W 3 OVFL 0 R/(W)* H'B7 2 CMFL 0 R/(W)* 1 OVIEL 0 R/W Timer F 0 CCLRL 0 R/W Timer overflow interrupt enable L 0 TCFL overflow interrupt disabled 1 TCFL overflow interrupt enabled Compare match flag L 0 [Clearing condition] After reading CMFL = 1, cleared by writing 0 to CMFL 1 [Setting condition] When the TCFL value matches the OCRFL value Timer overflow flag L 0 [Clearing condition] After reading OVFL = 1, cleared by writing 0 to OVFL 1 [Setting condition] When the value of TCFL goes from H'FF to H'00 Counter clear H 0 16-bit mode: 8-bit mode: 1 16-bit mode: 8-bit mode: TCF clearing by compare match disabled TCFH clearing by compare match disabled TCF clearing by compare match enabled TCFH clearing by compare match enabled Counter clear L 0 TCFL clearing by compare match disabled 1 TCFL clearing by compare match enabled Timer overflow interrupt enable H 0 TCFH overflow interrupt disabled 1 TCFH overflow interrupt enabled Compare match flag H 0 [Clearing condition] After reading CMFH = 1, cleared by writing 0 to CMFH 1 [Setting condition] When the TCFH value matches the OCRFH value Timer overflow flag H 0 [Clearing condition] After reading OVFH = 1, cleared by writing 0 to OVFH 1 [Setting condition] When the value of TCFH goes from H'FF to H'00 Note: * Only a write of 0 for flag clearing is possible. 426 TCFH--8-bit timer counter FH Bit Initial value Read/Write 7 TCFH7 0 R/W 6 TCFH6 0 R/W 5 TCFH5 0 R/W 4 TCFH4 0 R/W 3 H'B8 2 TCFH2 0 R/W 1 TCFH1 0 R/W Timer F 0 TCFH0 0 R/W TCFH3 0 R/W Count value TCFL--8-bit timer counter FL Bit Initial value Read/Write 7 TCFL7 0 R/W 6 TCFL6 0 R/W 5 TCFL5 0 R/W 4 TCFL4 0 R/W 3 H'B9 2 TCFL2 0 R/W 1 TCFL1 0 R/W Timer F 0 TCFL0 0 R/W TCFL3 0 R/W Count value OCRFH--Output compare register FH Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'BA 2 1 R/W 1 1 R/W Timer F 0 1 R/W OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL--Output compare register FL Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'BB 2 1 R/W 1 1 R/W Timer F 0 1 R/W OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 427 TMG--Timer mode register G Bit Initial value Read/Write 7 OVFH 0 R/(W)* 6 OVFL 0 R/(W)* 5 OVIE 0 R/W 4 IIEGS 0 R/W 3 H'BC 2 CCLR0 0 R/W 1 CKS1 0 R/W Timer G 0 CKS0 0 R/W CCLR1 0 R/W Counter clear 0 0 TCG is not cleared 1 TCG is cleared at the falling edge of the input capture signal 1 0 TCG is cleared at the rising edge of the input capture signal 1 TCG is cleared at both edges of the input capture signal Clock select 0 0 Internal clock: 1 Internal clock: 1 0 Internal clock: 1 Internal clock: o/64 o/32 o/2 o W /2 Input capture interrupt edge select 0 Interrupts are requested at the rising edge of the input capture signal 1 Interrupts are requested at the falling edge of the input capture signal Timer overflow interrupt enable 0 TCG overflow interrupt disabled 1 TCG overflow interrupt enabled Timer overflow flag L 0 [Clearing condition] After reading OVFL = 1, cleared by writing 0 to OVFL 1 [Setting condition] When the value of TCG goes from H'FF to H'00 Timer overflow flag H 0 [Clearing condition] After reading OVFH = 1, cleared by writing 0 to OVFH 1 [Setting condition] When the value of TCG goes from H'FF to H'00 Note: * Only a write of 0 for flag clearing is possible. 428 ICRGF--Input capture register GF Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'BD 2 0 R 1 0 R Timer G 0 0 R ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 ICRGR--Input capture register GR Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'BE 2 0 R 1 0 R Timer G 0 0 R ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 429 LPCR--LCD port control register Bit Initial value Read/Write 7 DTS1 0 R/W 6 DTS0 0 R/W 5 CMX 0 R/W 4 SGX 0 R/W 3 H'C0 2 LCD controller/driver 1 SGS1 0 R/W 0 SGS0 0 R/W SGS3 0 R/W SGS2 0 R/W Segment driver select Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Functions of Pins SEG40 to SEG 1 SEG36 to SEG32 to SEG28 to SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to SEG4 to SEG33 SEG29 SEG25 SEG21 SEG17 SEG13 SEG9 SEG5 SEG1 Remarks Port SEG SEG SEG SEG SEG SEG SEG SEG SEG Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port SEG SEG SEG SEG SEG SEG SEG Port Port Port SEG SEG SEG SEG SEG SEG SEG Port Port Port Port SEG SEG SEG SEG SEG SEG Port Port Port Port SEG SEG SEG SEG SEG SEG Port Port Port Port Port SEG SEG SEG SEG SEG Port Port Port Port Port SEG SEG SEG SEG SEG Port Port Port Port Port Port SEG SEG SEG SEG Port Port Port Port Port Port SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG Port Port Port Port Port Port Port Port SEG SEG Port Port Port Port Port Port Port Port SEG SEG Port Port Port Port Port Port Port Port Port SEG Port Port Port Port Port Port Port Port Port SEG (initial value) SEG40 to SGX SGS3 SGS2 SGS1 SGS0 SEG37 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 Port SEG SEG SEG SEG SEG SEG SEG SEG SEG * 0 * 0 0 1 1 0 0 1 External segment Port expansion External segment SEG expansion External segment SEG expansion External segment SEG expansion External segment SEG expansion External segment SEG expansion External segment SEG expansion External segment SEG expansion External segment SEG expansion External segment SEG expansion 1 0 1 1 0 0 1 1 0 1 1 * * 0 1 Expansion signal select 0 Pins SEG40 to SEG37 1 Pins CL 1 , CL 2 , DO, and M Duty and common function select Bit 7 Bit 6 Bit 5 Common Driver COM 1 COM 4 to COM 1 1/2 duty COM 2 , COM1 COM 4 to COM 1 1/3 duty COM 3 to COM 1 COM 4 to COM 1 1/4 duty COM 4 to COM 1 Other Uses COM3 , COM2 , and COM1 usable as ports COM4 , COM3 , and COM2 output the same waveform as COM 1 COM4 and COM 3 usable as ports COM4 outputs the same waveform as COM 3 , and COM 2 the same waveform as COM 1 COM4 usable as port COM4 outputs a non-select waveform -- DTS1 DTS0 CMX Duty 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 1 Static 430 LCR--LCD control register H'C1 LCD controller/driver Bit Initial value Read/Write 7 -- 1 -- 6 PSW 0 R/W 5 ACT 0 R/W 4 DISP 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Frame frequency select Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 0 0 0 * 1 1 * 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Display data control 0 Blank data displayed 1 LCD RAM data displayed Display active 0 LCD controller/driver operation stopped 1 LCD controller/driver operational Power switch 0 LCD power supply resistive voltage divider off 1 LCD power supply resistive voltage divider on Note: * Don't care Clock oW oW o W /2 o/2 o/4 o/8 o/16 o/32 o/64 o/128 o/256 Frame Frequency o = 5 MHz o = 625 Hz 128 Hz (initial value) 64 Hz 32 Hz -- 610 Hz -- 305 Hz -- 153 Hz 610 Hz 76.3 Hz 305 Hz 38.1 Hz 153 Hz -- 76.3 Hz -- 38.1 Hz -- 431 AMR--A/D mode register Bit Initial value Read/Write 7 CKS 0 R/W 6 TRGE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CH3 0 R/W H'C4 2 CH2 0 R/W 1 A/D converter 0 CH0 0 R/W CH1 0 R/W Channel select Bit 3 Bit 2 Bit 1 CH3 CH2 CH1 0 0 * 1 0 1 1 0 0 1 1 0 1 Bit 0 CH0 * 0 1 0 1 0 1 0 1 0 1 0 1 Analog input channel No channel selected AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 AN 8 AN 9 AN 10 AN 11 External trigger select 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select Bit 7 CKS Conversion Period 0 62/o 1 31/o Conversion Time o = 2 MHz o = 5 MHz 31 s 15.5 s 12.4 s -- *1 Notes: * Don't care 1. Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a value of at least 12.4 s. 432 ADRR--A/D result register Bit Initial value Read/Write 7 ADR7 R 6 ADR6 R 5 ADR5 R 4 ADR4 R 3 ADR3 R H'C5 2 ADR2 R 1 A/D converter 0 ADR0 R ADR1 R Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed A/D conversion result ADSR--A/D start register Bit Initial value Read/Write 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'C6 2 -- 1 -- A/D converter 1 -- 1 -- 0 -- 1 -- A/D status flag 0 Read Indicates the completion of A/D conversion Write Stops A/D conversion 1 Read Indicates A/D conversion in progress Write Starts A/D conversion 433 PMR1--Port mode register 1 H'C8 I/O ports Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 PWM 0 R/W 3 TMIG 0 R/W 2 TMOFH 0 R/W 1 TMOFL 0 R/W 0 TMOW 0 R/W P10 /TMOW pin function switch 0 Functions as P10 I/O pin 1 Functions as TMOW output pin P11 /TMOFL pin function switch 0 Functions as P11 I/O pin 1 Functions as TMOFL output pin P12 /TMOFH pin function switch 0 Functions as P12 I/O pin 1 Functions as TMOFH output pin P13 /TMIG pin function switch 0 Functions as P13 I/O pin 1 Functions as TMIG input pin P14 /PWM pin function switch 0 Functions as P14 I/O pin 1 Functions as PWM output pin P15 /IRQ 1 /TMIB pin function switch 0 Functions as P15 I/O pin 1 Functions as IRQ 1 /TMIB input pin P16 /IRQ 2 /TMIC pin function switch 0 Functions as P16 I/O pin 1 Functions as IRQ 2 /TMIC input pin P17 /IRQ 3 /TMIF pin function switch 0 Functions as P17 I/O pin 1 Functions as IRQ 3 /TMIF input pin 434 PMR2--Port mode register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 POF2 0 R/W 4 NCS 0 R/W 3 IRQ0 0 R/W H'C9 2 POF1 0 R/W 1 UD 0 R/W I/O ports 0 IRQ4 0 R/W P20 /IRQ 4 /ADTRG pin function switch 0 Functions as P20 I/O pin 1 Functions as IRQ 4 /ADTRG input pin P21 /UD pin function switch 0 Functions as P21 I/O pin 1 Functions as UD input pin P32 /SO 1 pin PMOS control 0 CMOS output 1 NMOS open-drain output P43 /IRQ 0 pin function switch 0 Functions as P4 3 I/O pin 1 Functions as IRQ 0 input pin TMIG noise canceller select 0 Noise canceller function not selected 1 Noise canceller function selected P35 /SO 2 pin PMOS control 0 CMOS output 1 NMOS open-drain output 435 PMR3--Port mode register 3 H'CA I/O ports Bit Initial value Read/Write 7 CS 0 R/W 6 STRB 0 R/W 5 SO2 0 R/W 4 SI2 0 R/W 3 SCK 2 0 R/W 2 SO12 0 R/W 1 SI1 0 R/W 0 SCK 1 0 R/W P3 0 /SCK 1 pin function switch 0 Functions as P3 0 I/O pin 1 Functions as SCK 1 I/O pin P3 1 /SI 1 pin function switch 0 Functions as P3 1 I/O pin 1 Functions as SI 1 input pin P3 2 /SO 1 pin function switch 0 Functions as P3 2 I/O pin 1 Functions as SO 1 output pin P33 /SCK 2 pin function switch 0 Functions as P3 3 I/O pin 1 Functions as SCK 2 I/O pin P34 /SI 2 pin function switch 0 Functions as P3 4 I/O pin 1 Functions as SI 2 input pin P35 /SO 2 pin function switch 0 Functions as P3 5 I/O pin 1 Functions as SO 2 output pin P36 /STRB pin function switch 0 Functions as P3 6 I/O pin 1 Functions as STRB output pin P37 /CS pin function switch 0 Functions as P3 7 I/O pin 1 Functions as CS input pin 436 PMR4--Port mode register 4 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'CB 2 0 R/W 1 0 R/W I/O ports 0 0 R/W NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 0 P2 n has CMOS output 1 P2 n has NMOS open-drain output PMR5--Port mode register 5 Bit Initial value Read/Write 7 WKP7 0 R/W 6 WKP6 0 R/W 5 WKP5 0 R/W 4 WKP4 0 R/W 3 WKP3 0 R/W H'CC 2 WKP2 0 R/W 1 WKP1 0 R/W I/O ports 0 WKP0 0 R/W P5n /WKPn /SEG n + 1 pin function switch 0 Functions as P5 n I/O pin 1 Functions as WKPn input pin RLCTR--LCD RAM relocation register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'CF 2 -- 1 -- 1 RLCT1 0 R/W 0 RLCT0 0 R/W 437 PWCR--PWM control register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'D0 2 -- 1 -- 1 -- 1 -- 14-bit PWM 0 PWCR0 0 W Clock select 0 The input clock is o/2 (to* = 2/o). The conversion period is 16,384/o, with a minimum modulation width of 1/o 1 The input clock is o/4 (to* = 4/o). The conversion period is 32,768/o, with a minimum modulation width of 2/o Note: * to: Period of PWM input clock PWDRU--PWM data register U Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W H'D1 2 0 W 1 0 W 14-bit PWM 0 0 W PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDUR1 PWDRU0 Upper 6 bits of data for generating PWM waveform PWDRL--PWM data register L Bit Initial value Read/Write 7 PWDRL7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'D2 2 0 W 1 0 W 14-bit PWM 0 0 W PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Lower 8 bits of data for generating PWM waveform 438 PDR1--Port data register 1 Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W H'D4 2 P12 0 R/W 1 P11 0 R/W I/O ports 0 P10 0 R/W PDR2--Port data register 2 Bit Initial value Read/Write 7 P27 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W H'D5 2 P22 0 R/W 1 P21 0 R/W I/O ports 0 P20 0 R/W PDR3--Port data register 3 Bit Initial value Read/Write 7 P37 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W H'D6 2 P32 0 R/W 1 P31 0 R/W I/O ports 0 P30 0 R/W PDR4--Port data register 4 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 P43 1 R H'D7 2 P42 0 R/W 1 P41 0 R/W I/O ports 0 P40 0 R/W PDR5--Port data register 5 Bit Initial value Read/Write 7 P5 7 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W H'D8 2 P52 0 R/W 1 P51 0 R/W I/O ports 0 P50 0 R/W 439 PDR6--Port data register 6 Bit Initial value Read/Write 7 P6 7 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W H'D9 2 P62 0 R/W 1 P61 0 R/W I/O ports 0 P60 0 R/W PDR7--Port data register 7 Bit Initial value Read/Write 7 P7 7 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 P73 0 R/W H'DA 2 P72 0 R/W 1 P71 0 R/W I/O ports 0 P70 0 R/W PDR8--Port data register 8 Bit Initial value Read/Write 7 P8 7 0 R/W 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W 3 P83 0 R/W H'DB 2 P82 0 R/W 1 P81 0 R/W I/O ports 0 P80 0 R/W PDR9--Port data register 9 Bit Initial value Read/Write 7 P9 7 0 R/W 6 P96 0 R/W 5 P95 0 R/W 4 P94 0 R/W 3 P93 0 R/W H'DC 2 P92 0 R/W 1 P91 0 R/W I/O ports 0 P90 0 R/W PDRA--Port data register A Bit Initial value Read/Write 7 -- 1 _ 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PA 3 0 R/W H'DD 2 PA 2 0 R/W 1 PA 1 0 R/W I/O ports 0 PA 0 0 R/W 440 PDRB--Port data register B Bit Initial value Read/Write R R R R R 7 PB 7 6 PB 6 5 PB 5 4 PB 4 3 PB 3 H'DE 2 PB 2 R 1 PB 1 R I/O ports 0 PB 0 R PDRC--Port data register C Bit Initial value Read/Write -- -- -- -- R 7 -- 6 -- 5 -- 4 -- 3 PC 3 H'DF 2 PC 2 R 1 PC 1 R I/O ports 0 PC 0 R PUCR1--Port pull-up control register 1 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E0 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 PUCR3--Port pull-up control register 3 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E1 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR3 7 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 PUCR5--Port pull-up control register 5 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E2 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 441 PUCR6--Port pull-up control register 6 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'E3 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR6 7 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 PCR1--Port control register 1 Bit Initial value Read/Write 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W H'E4 2 PCR12 0 W 1 PCR11 0 W I/O ports 0 PCR10 0 W Port 1 input/output select 0 Input pin 1 Output pin PCR2--Port control register 2 Bit Initial value Read/Write 7 PCR27 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 PCR23 0 W H'E5 2 PCR22 0 W 1 PCR21 0 W I/O ports 0 PCR20 0 W Port 2 input/output select 0 Input pin 1 Output pin 442 PCR3--Port control register 3 Bit Initial value Read/Write 7 PCR37 0 W 6 PCR36 0 W 5 PCR35 0 W 4 PCR34 0 W 3 PCR33 0 W H'E6 2 PCR32 0 W 1 PCR31 0 W I/O ports 0 PCR30 0 W Port 3 input/output select 0 Input pin 1 Output pin PCR4--Port control register 4 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'E7 2 PCR42 0 W 1 PCR41 0 W I/O ports 0 PCR40 0 W Port 4 input/output select 0 Input pin 1 Output pin PCR5--Port control register 5 Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W H'E8 2 PCR52 0 W 1 PCR51 0 W I/O ports 0 PCR50 0 W Port 5 input/output select 0 Input pin 1 Output pin 443 PCR6--Port control register 6 Bit Initial value Read/Write 7 PCR6 7 0 W 6 PCR6 6 0 W 5 PCR6 5 0 W 4 PCR6 4 0 W 3 H'E9 2 PCR6 2 0 W 1 PCR6 1 0 W I/O ports 0 PCR6 0 0 W PCR6 3 0 W Port 6 input/output select 0 Input pin 1 Output pin PCR7--Port control register 7 Bit Initial value Read/Write 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W H'EA 2 PCR72 0 W 1 PCR71 0 W I/O ports 0 PCR70 0 W Port 7 input/output select 0 Input pin 1 Output pin PCR8--Port control register 8 Bit Initial value Read/Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W H'EB 2 PCR82 0 W 1 PCR81 0 W I/O ports 0 PCR80 0 W Port 8 input/output select 0 Input pin 1 Output pin 444 PCR9--Port control register 9 Bit Initial value Read/Write 7 PCR97 0 W 6 PCR96 0 W 5 PCR95 0 W 4 PCR94 0 W 3 PCR93 0 W H'EC 2 PCR92 0 W 1 PCR91 0 W I/O ports 0 PCR90 0 W Port 9 input/output select 0 Input pin 1 Output pin PCRA--Port control register A Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 H'ED 2 PCRA 2 0 W 1 PCRA 1 0 W I/O ports 0 PCRA 0 0 W PCRA 3 0 W Port A input/output select 0 Input pin 1 Output pin 445 SYSCR1--System control register 1 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 H'F0 2 -- 1 -- System control 1 -- 1 -- 0 -- 1 -- LSON 0 R/W Low speed on flag 0 The CPU operates on the system clock (o) 1 The CPU operates on the subclock (oSUB ) Standby timer select 2 to 0 0 0 0 Wait time = 8,192 states 1 Wait time = 16,384 states 1 0 Wait time = 32,768 states 1 Wait time = 65,536 states 1 * * Wait time = 131,072 states Software standby 0 When a SLEEP instruction is executed in active mode, a transition is made to sleep mode. When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode. 1 When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode. When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode. Note: * Don't care 446 SYSCR2--System control register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 NESEL 0 R/W 3 H'F1 2 MSON 0 R/W System control 1 SA1 0 R/W 0 SA0 0 R/W DTON 0 R/W Medium speed on flag 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct transfer on flag Subactive mode clock select 0 0 o W /8 1 o W /4 1 * o W /2 0 When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. 1 When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1. Noise elimination sampling frequency select 0 Sampling rate is oOSC /16 1 Sampling rate is oOSC /4 Note: * Don't care 447 IEGR--IRQ edge select register H'F2 System control Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 IEG4 0 R/W 3 IEG3 0 R/W 2 IEG2 0 R/W 1 IEG1 0 R/W 0 IEG0 0 R/W IRQ 0 edge select 0 Falling edge of IRQ 0 pin input is detected 1 Rising edge of IRQ 0 pin input is detected IRQ 1 edge select 0 Falling edge of IRQ 1 /TMIB pin input is detected 1 Rising edge of IRQ 1 /TMIB pin input is detected IRQ 2 edge select 0 Falling edge of IRQ 2 /TMIC pin input is detected 1 Rising edge of IRQ 2 /TMIC pin input is detected IRQ 3 edge select 0 Falling edge of IRQ 3 /TMIF pin input is detected 1 Rising edge of IRQ 3 /TMIF pin input is detected IRQ 4 edge select 0 Falling edge of IRQ 4 /ADTRG pin input is detected 1 Rising edge of IRQ 4 /ADTRG pin input is detected 448 IENR1--Interrupt enable register 1 H'F3 System control Bit Initial value Read/Write 7 IENTA 0 R/W 6 IENS1 0 R/W 5 IENWP 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W 2 IEN2 0 R/W 1 IEN1 0 R/W 0 IEN0 0 R/W IRQ 4 to IRQ 0 interrupt enable 0 Disables interrupt request IRQ n 1 Enables interrupt request IRQ n Wakeup interrupt enable (n = 4 to 0) 0 Disables interrupt requests from WKP7 to WKP0 1 Enables interrupt requests from WKP7 to WKP0 SCI1 interrupt enable 0 Disables SCI1 interrupts 1 Enables SCI1 interrupts Timer A interrupt enable 0 Disables timer A interrupts 1 Enables timer A interrupts 449 IENR2--Interrupt enable register 2 H'F4 System control Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 IENS2 0 R/W 4 IENTG 0 R/W 3 0 R/W 2 0 R/W 1 IENTC 0 R/W 0 IENTB 0 R/W IENTFH IENTFL Timer B interrupt enable 0 Disables timer B interrupts 1 Enables timer B interrupts Timer C interrupt enable 0 Disables timer C interrupts 1 Enables timer C interrupts Timer FL interrupt enable 0 Disables timer FL interrupts 1 Enables timer FL interrupts Timer FH interrupt enable 0 Disables timer FH interrupts 1 Enables timer FH interrupts Timer G interrupt enable 0 Disables timer G interrupts 1 Enables timer G interrupts SCI2 interrupt enable 0 Disables SCI2 interrupts 1 Enables SCI2 interrupts A/D converter interrupt enable 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Direct transfer interrupt enable 0 Disables direct transfer interrupt requests 1 Enables direct transfer interrupt requests 450 IRR1--Interrupt request register 1 Bit Initial value Read/Write 7 IRRTA 0 R/W * 6 IRRS1 0 R/W * 5 -- 1 -- 4 IRRI4 0 R/W * 3 H'F6 2 IRRI2 0 R/W * System control 1 IRRI1 0 R/W * 0 IRRI0 0 R/W * IRRI3 0 R/W * IRQ 4 to IRQ 0 interrupt request flag 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 1 [Setting condition] When pin IRQ n is set to interrupt input and the designated signal edge is detected SCI1 interrupt request flag 0 [Clearing condition] When IRRS1 = 1, it is cleared by writing 0 1 [Setting condition] When an SCI1 transfer is completed Timer A interrupt request flag 0 [Clearing condition] When IRRTA = 1, it is cleared by writing 0 1 [Setting condition] When the timer A counter overflows from H'FF to H'00 Note: * Only a write of 0 for flag clearing is possible. (n = 4 to 0) 451 IRR2--Interrupt request register 2 Bit Initial value Read/Write 7 IRRDT 0 R/W * 6 IRRAD 0 R/W * 5 IRRS2 0 R/W * 4 IRRTG 0 R/W * 3 0 R/W * H'F7 2 0 R/W * System control 1 IRRTC 0 R/W * 0 IRRTB 0 R/W * IRRTFH IRRTFL Timer B interrupt request flag 0 [Clearing condition] When IRRTB = 1, it is cleared by writing 0 1 [Setting condition] When the timer B counter overflows from H'FF to H'00 Timer C interrupt request flag 0 [Clearing condition] When IRRTC = 1, it is cleared by writing 0 1 [Setting condition] When the timer C counter overflows from H'FF to H'00 or underflows from H'00 to H'FF Timer FL interrupt request flag 0 [Clearing condition] When IRRTFL = 1, it is cleared by writing 0 1 [Setting condition] When counter FL matches output compare register FL in 8-bit mode Timer FH interrupt request flag 0 [Clearing condition] When IRRTFH = 1, it is cleared by writing 0 1 [Setting condition] When counter FH matches output compare register FH in 8-bit mode, or when 16-bit counter F (TCFL, TCFH) matches 16-bit output compare register F (OCRFL, OCRFH) in 16-bit mode Timer G interrupt request flag 0 [Clearing condition] When IRRTG = 1, it is cleared by writing 0 1 [Setting condition] When pin TMIG is set to TMIG input and the designated signal edge is detected SCI2 interrupt request flag 0 [Clearing condition] When IRRS2 = 1, it is cleared by writing 0 1 [Setting condition] When an SCI2 transfer is completed or aborted A/D converter interrupt request flag 0 [Clearing condition] When IRRAD = 1, it is cleared by writing 0 1 [Setting condition] When A/D conversion is completed and ADSF is reset Direct transfer interrupt request flag 0 [Clearing condition] When IRRDT = 1, it is cleared by writing 0 1 [Setting condition] A SLEEP instruction is executed when DTON = 1 and a direct transfer is made Note: * Only a write of 0 for flag clearing is possible. 452 IWPR--Wakeup interrupt request register Bit Initial value Read/Write 7 IWPF7 0 R/W * 6 IWPF6 0 R/W * 5 IWPF5 0 R/W * 4 IWPF4 0 R/W * 3 H'F9 2 IWPF2 0 R/W * System control 1 IWPF1 0 R/W * 0 IWPF0 0 R/W * IWPF3 0 R/W * Wakeup interrupt request flag 0 [Clearing condition] When IWPFn = 1, it is cleared by writing 0 1 [Setting condition] When pin WKP n is set to interrupt input and a falling signal edge is detected (n = 7 to 0) Note: * Only a write of 0 for flag clearing is possible. 453 Appendix C I/O Port Block Diagrams C.1 Schematic Diagram of Port 1 SBY (low level during reset and in standby mode) Internal data bus PUCR1n VCC VCC PMR1n P1n PDR1n VSS PCR1n IRQ n - 4 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 n = 5 to 7 Figure C-1 (a) Port 1 Block Diagram (Pins P17 to P15) 454 PWM module PWM SBY Internal data bus PUCR14 VCC PMR14 P14 PDR14 VCC VSS PCR14 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (b) Port 1 Block Diagram (Pin P14) 455 SBY Internal data bus PUCR13 VCC VCC PMR13 P13 PDR13 VSS PCR13 Timer G module TMIG PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (c) Port 1 Block Diagram (Pin P13) 456 Timer F module TMOFH (P12 ) TMOFL (P1 1 ) SBY Internal data bus PUCR1n VCC PMR1n P1n PDR1n VCC VSS PCR1n PDR1: PCR1: PMR1: PUCR1: n = 2, 1 Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (d) Port 1 Block Diagram (Pins P12 and P11) 457 Timer A module TMOW SBY Internal data bus PUCR10 VCC PMR10 P10 PDR10 VCC VSS PCR10 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (e) Port 1 Block Diagram (Pin P10) 458 C.2 Schematic Diagram of Port 2 Internal data bus SBY PMR4 n VCC P2n PDR2 n VSS PCR2 n PDR2: PCR2: PMR4: Port data register 2 Port control register 2 Port mode register 4 n = 2 to 7 Figure C-2 (a) Port 2 Block Diagram (Pins P27 to P22) 459 SBY Internal data bus PMR4 1 VCC PMR21 P21 PDR21 VSS PCR21 Timer C module UD PDR2: PCR2: PMR2: PMR4: Port data register 2 Port control register 2 Port mode register 2 Port mode register 4 Figure C-2 (b) Port 2 Block Diagram (Pin P21) 460 SBY Internal data bus PMR4 0 VCC PMR2 0 P20 PDR20 VSS PCR2 0 IRQ 4 PDR2: PCR2: PMR2: PMR4: Port data register 2 Port control register 2 Port mode register 2 Port mode register 4 Figure C-2 (c) Port 2 Block Diagram (Pin P20) 461 C.3 Schematic Diagram of Port 3 SBY Internal data bus PUCR37 VCC VCC PMR3 7 P3 7 PDR3 7 VSS PCR3 7 SCI2 module CS PDR3: PCR3: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Figure C-3 (a) Port 3 Block Diagram (Pin P37) 462 SCI2 module STRB SBY Internal data bus PUCR3 6 VCC PMR3 6 P3 6 PDR3 6 VCC VSS PCR3 6 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C-3 (b) Port 3 Block Diagram (Pin P36) 463 SCI2 module HZS02N SO 2 SBY PMR2 5 Internal data bus PUCR35 VCC PMR3 5 P3 5 PDR3 5 VCC VSS PCR3 5 PDR3: PCR3: PMR3: PMR2: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port mode register 2 Port pull-up control register 3 Figure C-3 (c) Port 3 Block Diagram (Pin P35) 464 SBY Internal data bus PUCR3n VCC VCC PMR3 n P3 n PDR3 n VSS PCR3 n SCI module SI PDR3: PCR3: PMR3: PUCR3: n = 1, 4 Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Figure C-3 (d) Port 3 Block Diagram (Pins P34 and P31) 465 SCI module EXCK SCKO SCKI SBY PUCR3n VCC PMR3 n P3 n PDR3n Internal data bus VCC VSS PCR3n PDR3: PCR3: PMR3: PUCR3: n = 3, 0 Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Figure C-3 (e) Port 3 Block Diagram (Pins P33 and P30) 466 SCI1 module SO 1 PMR2 2 Internal data bus PUCR32 VCC PMR3 2 P3 2 PDR3 2 SBY VCC VSS PCR3 2 PDR3: PCR3: PMR3: PMR2: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port mode register 2 Port pull-up control register 3 Figure C-3 (f) Port 3 Block Diagram (Pin P32) 467 C.4 Schematic Diagram of Port 4 Internal data bus PMR2 3 P4 3 IRQ 0 PMR2: Port mode register 2 Figure C-4 (a) Port 4 Block Diagram (Pin P43) SBY VCC SCI3 module TE TXD P4 2 PDR4 2 Internal data bus VSS PCR4 2 PDR4: PCR4: Port data register 4 Port control register 4 Figure C-4 (b) Port 4 Block Diagram (Pin P42) 468 SBY SCI3 module VCC RE RXD P4 1 PDR4 1 Internal data bus VSS PCR4 1 PDR4: Port data register 4 PCR4: Port control register 4 Figure C-4 (c) Port 4 Block Diagram (Pin P41) 469 SBY SCI3 module VCC SCKIE SCKOE SCKO SCKI P4 0 PDR4 0 Internal data bus VSS PCR4 0 PDR4: Port data register 4 PCR4: Port control register 4 Figure C-4 (d) Port 4 Block Diagram (Pin P40) 470 C.5 Schematic Diagram of Port 5 SBY Internal data bus PUCR5n VCC VCC PMR5 n P5 n PDR5n VSS PCR5n WKPn PDR5: PCR5: PMR5: PUCR5: Port data register 5 Port control register 5 Port mode register 5 Port pull-up control register 5 n = 0 to 7 Figure C-5 Port 5 Block Diagram 471 C.6 Schematic Diagram of Port 6 SBY Internal data bus PUCR6n VCC VCC P6 n PDR6n VSS PCR6n PDR6: Port data register 6 PCR6: Port control register 6 PUCR4: Port pull-up control register 6 n = 0 to 7 Figure C-6 Port 6 Block Diagram 472 C.7 Schematic Diagram of Port 7 SBY Internal data bus VCC PDR7n P7 n PCR7n VSS PDR7: PCR7: Port data register 7 Port control register 7 n = 0 to 7 Figure C-7 Port 7 Block Diagram 473 C.8 Schematic Diagram of Port 8 SBY Internal data bus VCC PDR8 n P8 n PCR8 n VSS PDR8: Port data register 8 PCR8: Port control register 8 n = 0 to 7 Figure C-8 Port 8 Block Diagram 474 C.9 Schematic Diagram of Port 9 SBY Internal data bus VCC PDR9n P9n PCR9n VSS PDR9: Port data register 9 PCR9: Port control register 9 n = 0 to 7 Figure C-9 Port 9 Block Diagram 475 C.10 Schematic Diagram of Port A SBY Internal data bus VCC PDRA n PAn PCRA n VSS PDRA: Port data register A PCRA: Port control register A n = 0 to 3 Figure C-10 Port A Block Diagram 476 C.11 Schematic Diagram of Port B Internal data bus PBn A/D module DEC AMR0 to AMR3 V IN n = 0 to 7 Figure C-11 Port B Block Diagram C.12 Schematic Diagram of Port C Internal data bus PCn A/D module DEC AMR0 to AMR3 V IN n = 0 to 3 Figure C-12 Port C Block Diagram 477 Appendix D Port States in the Different Processing States Table D-1 Port States Overview Port Reset Sleep Subsleep Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Watch Subactive Active Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Retained P17 to P10 High impedance P27 to P20 High Retained impedance P37 to P30 High Retained impedance P43 to P40 High Retained impedance P57 to P50 High Retained impedance Retained P67 to P60 High impedance P77 to P70 High Retained impedance P87 to P80 High Retained impedance P97 to P90 High Retained impedance PA3 to PA0 High Retained impedance High Retained impedance* High Retained impedance High Retained impedance* High Retained impedance High Retained impedance* High Retained impedance* High Retained impedance High Retained impedance High Retained impedance High Retained impedance PB7 to PB0 High High High High High High High impedance impedance impedance impedance impedance impedance impedance PC3 to PC0 High High High High High High High impedance impedance impedance impedance impedance impedance impedance Note: * High level output when MOS pull-up is in on state. 478 Appendix E Product Code Lineup Table E-1 H8/3834U Series Product Code Lineup Package (Hitachi Package Code) 100-pin QFP (FP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) Product Type H8/3837U ZTAT version Product Code Mark Code Order Code Name HD6473837UH HD6473837UF HD6473837UX Standard HD6473837UH HD6473837UH products HD6473837UF HD6473837UX HD6473837UF HD6473837UX Mask ROM version Standard HD6433837UH HD6433837U(***)H HD6433837U(***)H 100-pin QFP products (FP-100B) HD6433837UF HD6433837UX HD6433837U(***)F HD6433837U(***)F 100-pin QFP (FP-100A) HD6433837U(***)X HD6433837U(***)X 100-pin TQFP (TFP-100B) H8/3836U Mask ROM version Standard HD6433836UH HD6433836U(***)H HD6433836U(***)H 100-pin QFP products (FP-100B) HD6433836UF HD6433836UX HD6433836U(***)F HD6433836U(***)F 100-pin QFP (FP-100A) HD6433836U(***)X HD6433836U(***)X 100-pin TQFP (TFP-100B) H8/3835U Mask ROM version Standard HD6433835UH HD6433835U(***)H HD6433835U(***)H 100-pin QFP products (FP-100B) HD6433835UF HD6433835UX HD6433835U(***)F HD6433835U(***)F 100-pin QFP (FP-100A) HD6433835U(***)X HD6433835U(***)X 100-pin TQFP (TFP-100B) HD6473834UH HD6473834UF HD6473834UX 100-pin QFP (FP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) H8/3834U ZTAT version Standard HD6473834UH HD6473834UH products HD6473834UF HD6473834UX HD6473834UF HD6473834UX 479 Table E-1 H8/3834U Series Product Code Lineup (cont) Package (Hitachi Package Code) Product Type H8/3834U Mask ROM version Product Code Mark Code Order Code Name Standard HD6433834UH HD6433834U(***)H HD6433834U(***)H 100-pin QFP products (FP-100B) HD6433834UF HD6433834UX HD6433834U(***)F HD6433834U(***)F 100-pin QFP (FP-100A) HD6433834U(***)X HD6433834U(***)X 100-pin TQFP (TFP-100B) H8/3833U Mask ROM version Standard HD6433833UH HD6433833U(***)H HD6433833U(***)H 100-pin QFP products (FP-100B) HD6433833UF HD6433833UX HD6433833U(***)F HD6433833U(***)F 100-pin QFP (FP-100A) HD6433833U(***)X HD6433833U(***)X 100-pin TQFP (TFP-100B) Note: 1. (***) in mask ROM versions is the ROM code. 480 Appendix F Package Dimensions Dimensional drawings of H8/3834U Series packages FP-100B, FP-100A, and TFP-100B are shown in figures F-1, F-2, and F-3 below. unit: mm 0.5 mm Pitch 16.0 0.3 14 75 76 16.0 0.3 51 50 0.5 100 1 0.20 0.10 0.08 M 25 26 3.05 Max +0.20 -0.16 2.70 +0.08 -0.05 0.17 1.0 0 - 10 0.50 0.20 Hitachi code JEDEC code EIAJ code Weight (g) FP-100B - SC-595-D - 0.10 Figure F-1 FP-100B Package Dimensions 0.12 481 unit: mm 0.65 mm Pitch 80 81 18.8 0.4 14.0 24.8 0.4 20.0 51 50 0.65 100 1 0.30 0.10 30 0.13 M 31 0.17 0.05 3.10 Max 2.70 -0.16 +0.20 2.40 0 - 10 0.20 1.20 0.20 0.15 Hitachi code JEDEC code EIAJ code Weight (g) FP-100A - SC-580-J - Figure F-2 FP-100A Package Dimensions 482 unit: mm 0.5 mm Pitch 16.0 0.2 14.0 75 76 16.0 0.2 51 50 0.50 100 1 0.20 0.05 1.00 25 0.08 M 0.17 0.05 1.20 Max 26 0 - 5 0.50 0.10 0.10 0.00 Min 0.20 Max Hitachi code JEDEC code EIAJ code Weight (g) TFP-100B - - - Figure F-3 TFP-100B Package Dimensions Note: In case of inconsistencies arising within figures, dimensional drawings listed in the Hitachi Semiconductor Packages Manual take precedence and are considered correct. 483 H8/3834U Series Hardware Manual Publication Date: Published by: 1st Edition, September 1995 Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Document Center Hitachi Microcomputer System Ltd. Copyright (c) Hitachi, Ltd., 1995. All rights reserved. Printed in Japan. |
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